Electrical Characterization of $\hbox{Al}_{2} \hbox{O}_{3}$/n-InAs Metal–Oxide–Semiconductor Capacitors With Various Surface Treatments

Low interface trap density Al2O3/In0.53Ga0.47As MOS capacitor fabricated on MOCVD-grown InGaAs epitaxial layer on Si substrate

“…Table Ishows the comparison of D it values for the three samples with different doping concentrations and with PDA at 400 and 500°C. The similar D it distribution with comparable mid-gap (above E v 0.3 to 0.42 eV) D it values of 5.5 © 10 11 cm ¹2 eV ¹1 for the MOSCAPs on the Si substrate and the In 0.53 Ga 0.47 As MOSCAPs on the InP substrate indicates that the qualities of the In 0.53 Ga 0.47 As layer on the Si substrate in this study and the In 0.53 Ga 0.47 As layer grown on the InP substrate in previous reports are the same 23). D it increased when the PDA temperature was increased to 500°C; this phenomenon is consistent with the results of the XPS spectra.…”

Atomic layer deposited Al2O3 passivation of type II InAs/GaSb superlattice photodetectors

“…7 Reduction of oxides after Al 2 O 3 deposition for GaSb and InAs has been confirmed by XPS measurements. 11,12,25 Finally, in the case of T2SLs with large numbers of very thin dissimilar layers, different etch rates of InAs and GaSb lead to roughness on the mesa side walls. Conformal coating of atomic layer deposition creates a perfect protective layer against environmental effects especially against oxidation.…”

Low Trap Density in InAs/High-k Nanowire Gate Stacks with Optimized Growth and Doping Conditions

“…To enable detailed analysis and optimized strategies for the gate stack, accurate techniques to characterize the nanowire/high- k interface are necessary. The most widely used method to study D it is the C – V technique. − However, a severe limitation is encountered in the vertical wrap-gated nanowire geometry due to the large incident parasitic capacitance during the device fabrication. Although some C – V studies of the structure have been reported recently, , the solutions to suppress the parasitic capacitance were all based on tailoring the device design via the use of either comparably thick isolation layers with long nanowires or plasma enhanced doping of the entire device region followed by selective etching the nanowire surface .…”

“…Here it is important to brief how trap states influence the device C – V modulation. When depleting the channel (following the green arrows), the Fermi level is moved from the conduction band edge toward the valence band, during which D it increases dramatically for InAs. − This first leads to a C – V curve stretching since larger negative biases are needed to discharge these filled trap states. Besides, it is also manifested by an increase in the capacitance minimum since an additional capacitance C it , due to the trap response, is added to the intrinsic capacitance at each dc bias.…”