Electrical characteristics of n-type vertically stacked nanowires operating up to 600 K

Mariniello, Genaro; Barraud, S.; Vinet, M.; Cassé, M.; Faynot, O.; Calcade, Jaime; Pavanello, Marcelo Antonio

doi:10.1016/j.sse.2022.108337

Cited by 5 publications

(2 citation statements)

References 14 publications

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“…The temperature increase promoted a linear VTH decrease. The threshold voltage reduction is caused by the rise of intrinsic carrier concentration (ni) at higher temperatures, reducing the Fermi potential (F) and the flatband voltage [24]. The width reduction increases the threshold voltage due to strong potential coupling between the top and sidewall gates.…”

Section: Device Characteristicsmentioning

confidence: 99%

High Temperature and Width Influence on the GIDL of Nanowire and Nanosheet SOI nMOSFETs

Souza

Cerdeira

Estrada

et al. 2023

IEEE J. Electron Devices Soc.

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In this work, an experimental evaluation of Gate-Induce Drain Leakage (GIDL) current is presented for nanowire and nanosheet-based SOI transistors. The effects of fin width and temperature increase are studied. Obtained results indicate that the increase in device width makes the GIDL current more sensitive to temperature increase. Three-dimensional numerical simulations have shown that despite the reverse junction leakage increase with temperature, leakage current in nanosheet and nanowire transistors is composed predominantly of GIDL current. The change in valence and conduction bands caused by temperature increase favors the band-to-band tunneling, which is responsible for the worsening of GIDL at high temperatures.

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Section: Device Characteristicsmentioning

confidence: 99%

High Temperature and Width Influence on the GIDL of Nanowire and Nanosheet SOI nMOSFETs

Souza

Cerdeira

Estrada

et al. 2023

IEEE J. Electron Devices Soc.

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“…The results of VTH versus temperature are presented in Figure 15. The threshold voltage has shown a linear decrease with temperature rise, due to the increase of intrinsic carrier concentration at higher temperatures, reducing the Fermi potential and the flatband voltage [32]. As narrower the fin, the larger the threshold voltage, due to the stronger potential coupling between the top and sidewall gates.…”

Section: Operation From 300 K Up To 580 Kmentioning

confidence: 99%

Performance of SOI Ω-Gate Nanowires from Cryogenic to High Temperatures

Pavanello

Souza

2022

JICS

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This review paper presents the electrical characteristics of Silicon-On-Insulator Ω-Gate nanowires in a wide range of temperatures. The operation in cryogenic and high-temperature environments will be experimentally explored. The influence of nanowire width and channel length will be discussed. Nanowires with and without strain will be investigated from room temperature down to cryogenic ones, showing that strained nanowires improve carrier mobility in the whole temperature range. At high temperatures, it is demonstrated that nanowires can operate successfully up to 580 K, maintaining the ideal body factor. The effect of high temperatures on Gate-Induced Drain Leakage will also be studied. The experimental results in the whole temperature range confirm that SOI nanowires are an excellent alternative for FinFET replacement in future technological nodes.

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Experimental assessment of gate-induced drain leakage in SOI stacked nanowire and nanosheet nMOSFETs at high temperatures

Souza¹,

Cerdeira²,

Estrada³

et al. 2023

Solid-State Electronics

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Electrical characteristics of n-type vertically stacked nanowires operating up to 600 K

Cited by 5 publications

References 14 publications

High Temperature and Width Influence on the GIDL of Nanowire and Nanosheet SOI nMOSFETs

High Temperature and Width Influence on the GIDL of Nanowire and Nanosheet SOI nMOSFETs

Performance of SOI Ω-Gate Nanowires from Cryogenic to High Temperatures

Experimental assessment of gate-induced drain leakage in SOI stacked nanowire and nanosheet nMOSFETs at high temperatures

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