Efficient Test Compression Technique for SoC Based on Block Merging and Eight Coding

Wu, Tiebin; Liu, Hengzhu; Liu, Peng-Xia

doi:10.1007/s10836-013-5415-7

Cited by 21 publications

(12 citation statements)

References 29 publications

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“…The results corresponding to different encoding schemes and the proposed HBMT are presented in Table 5. The comparisons are made between the proposed techniques and other schemes such as Golomb [16], FDR [17], EFDR [18], 9C [20], BM [21], CCPRL [26], 2 n −PRL [22], BM-8C [23]. Row ten of Table 5 represents the improvement obtained in application of HBMT in comparison with various techniques mentioned in the respective columns.…”

Section: Simulation Resultsmentioning

confidence: 99%

“…As evident from the experimental results, the test application time too is reduced using this scheme. Table 7 Comparison of test application time achieved between the proposed compression schemes and various other techniques in ATEclk Circuits α FDR [17] EFDR [18] BM [21] BM-8C [23] HBMT S5378 2 24,933 17,075 16,018 15,088 14,100 4 16,803 13,172 12,239 11,191 10,196 6 15,259 12,096 11,183 10,348 9824 8 14,039 11,652 10,899 10,089 9100 S9234 2 42,039 26,129 26,336 24,281 23,644 4 29,206 21,424 20,828 18,410 16,128 6…”

Section: Resultsmentioning

confidence: 99%

“…This paper presented fixed and variable length 9C compression techniques, which improves the compression considerably, but the restriction of merging only two sub‐blocks while encoding the test data limits the amount of achievable compression. Inter‐block‐merging‐based run‐length techniques such as block merging (BM) [21], 2 n compatible [22], BM‐8C [23], internal pattern run‐length code [24], variable pattern run length (VPRL) [25], count compatible run length (CCPRL) [26] etc. improve the compression efficiency by merging equal length compatible blocks.…”

Section: Related Work Of Code‐based Test Compressionmentioning

confidence: 99%

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Test data compression using hierarchical block merging technique

Vohra

Singh

2018

IET Computers & Digital Techniques

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Manufacturing of semiconductor devices at the sub-micron level has led to the introduction of huge number of faults. To ensure the quality of integrated circuits (ICs), enormous amount of test data is needed which, in turn, increases the overall test cost of the ICs. This study presents a hierarchical block-merging-based technique (HBMT) for test data compression, which appropriately encodes the test pattern blocks of fixed sizes at inter-and intra-block levels using lesser number of bits. The proposed technique works in four steps: segmentation of the entire length of test data into equal length blocks; categorisation of test blocks as compatible blocks and unique blocks; merging of compatible blocks to form representative pattern block, which is further merged at sub-block level; and compression of the non-compatible (unique) blocks using different encoding cases. Experimental results performed on various international symposium for circuits and systems (ISCAS)' 89 benchmark circuits demonstrate the effectiveness of the proposed test data compression technique. It is found that application of HBMT can improve the compression efficiency by an average of 73% along with a reduction in the test application time. This study also presents the decoder architecture.

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Section: Simulation Resultsmentioning

confidence: 99%

Section: Resultsmentioning

confidence: 99%

Section: Related Work Of Code‐based Test Compressionmentioning

confidence: 99%

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Test data compression using hierarchical block merging technique

Vohra

Singh

2018

IET Computers & Digital Techniques

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“…The Huffman encoding algorithm encodes frequently occurring symbols with shorter code words and on the other hand, least frequent ones are assigned relatively longer code. Other instances of such 'fixed' category are selective Huffman coding (SHC) [3] and optimal selective Huffman coding (OSHC) [4], dictionary-based coding [5] and block merging coding [6] and so on. Single run-length and double run-length encoding method fall in the category of 'variable' scheme.…”

Section: Introductionmentioning

confidence: 99%

A SoC-IP Core Test Data Compression Scheme based on Error Correcting Hamming Codes

Mitra¹,

Das²

2018

IJEECS

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As system-on-chip (SoC) integration is growing very rapidly, increased circuit densities in SoC have lead a radical increase in test data volume and reduction of this large test data volume is one of the biggest challenges in the testing industry. This paper presents an efficient test independent compression scheme primarily based on the error correcting Hamming codes. The scheme operates on the pre-computed test data without the need of structural information of the circuit under test and thus it is applicable for IP cores in SoC. Test vectors are equally sliced into the size of ‘n’ bits. Individual slices are treated as a Hamming codeword consisting of ‘p’ parity bits and ‘d’ data bits (n = d + p) and validity of each codeword is verified. If a valid slice is encountered’ data bits prefixed by ‘1’ are written to the compressed file, while for a non-valid slice all ‘n’ bits preceded by ‘0’ are written to the compressed file. Finally, we apply Huffman coding and RLE in order to improve the compression ratio further The efficiency of the proposed hybrid scheme is verified with the experimental outcomes and comparisons to existing compression methods suitable for testing of IP cores.

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“…The idea with a Huffman code is to encode symbols that occur more frequently with shorter code words and symbols that occur less frequently with longer code words, such as selective Huffman coding (SHC) [4] and optimal selective Huffman coding (OSHC) [5]. Other "fixed" schemes include dictionarybased coding [6] and block merging coding [7] and so on. Many bits in test set are don't care bits, which can be filled with any value (0 or 1) without decreasing the fault coverage of CUT.…”

Section: Introductionmentioning

confidence: 99%

A novel test data compression approach based on bit reversion

Cai

Zhou

Liu

et al. 2017

IEICE Electron. Express

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Test data compression is an effective methodology for reducing test data volume and testing time. This paper presents a new test data compression approach based on bit reversion, which compresses data more easier by reversing some test data bits without changing the fault coverage. As there are some don't care bits in test set, when they are filled, many faults will be repeatedly detected with multiple vectors. Correspondingly, a lot of bits in the test set can be modified without affecting the fault coverage. Experimental results show that the proposed method can increase compression ratio of code-based schemes by around 10%.

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Efficient Test Compression Technique for SoC Based on Block Merging and Eight Coding

Cited by 21 publications

References 29 publications

Test data compression using hierarchical block merging technique

Test data compression using hierarchical block merging technique

A SoC-IP Core Test Data Compression Scheme based on Error Correcting Hamming Codes

A novel test data compression approach based on bit reversion

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