A novel test data compression approach based on bit reversion

Cai, Shuo; Zhou, Yinbo; Liu, Peng; Yu, Fei; Wang, Wei

doi:10.1587/elex.14.20170502

Cited by 3 publications

(3 citation statements)

References 15 publications

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“…The sum of the uncompressible values of each scan flip-flop is shown in Equation ( 1). The probability ranking calculation of SFFs is shown in Equation (2). The calculation of the occurrence of the scan cell in the percentage of test pattern count is shown in Equation ( 3).…”

Section: Endmentioning

confidence: 99%

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New scan compression approach to reduce the test data volume

Shantagiri

Kapur

Shastry

2021

IET Computers & Digital Tech

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The test data volume (TDV) increases with increased target compression in scan compression and adds to the test cost. Increased TDV is the result of a dependency across scan flip‐flops (SFFs) that resulted from compression architecture, which is absent in scan mode. The SFFs have uncompressible values logic‐0 and logic‐1 in many or most of the patterns contribute to the TDV. In the proposed new scan compression (NSC) architecture, SFFs are analysed from Automatic Test Pattern Generation (ATPG) patterns generated in a scan mode. The identification of SFFs to be moved out of the compression architecture is carried out based on the NSC. The method includes a ranking of SFFs based on the specified values present in the test patterns. The SFFs having higher specified values are moved out of the compression architecture and placed in the outside scan chain. The NSC is the combination of scan compression and scan mode. This method decides the percentage (%) of SFFs to be moved out of compression architecture and is less than 0.5% of the total SFFs present in the design to achieve a better result. The NSC reduces dependencies across the SFFs present in the test compression architecture. It reduces the TDV and test application time. The results show a significant reduction in the TDV up to 78.14% for the same test coverage.

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Section: Endmentioning

confidence: 99%

“…Each symbol represents a certain group of bits to form the compressed test pattern. In [2], bit reversion‐based scan compression architecture is proposed. This method flips some of the specified bits of the test pattern.…”

Section: Introductionmentioning

confidence: 99%

New scan compression approach to reduce the test data volume

Shantagiri

Kapur

Shastry

2021

IET Computers & Digital Tech

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“…The design-for-test (DFT) based on the scan chain is one of the most widely used technologies in this field [3,4]. Moreover, despite the increase in the chip integration scale of the system-on-chip (SoC), the number of chip pins that can be used for testing remains limited, leading to the gradual increase of SoC testing difficulty and testing costs [5,6]. Therefore, lowcost testing technology has become a hot topic in the DFT of SoCs.…”

Section: Introductionmentioning

confidence: 99%

Test Stimuli Segmentation and Coding Method

2018

Teh. vjesn.

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Test vector coding and data transmission are the key technologies in the design-for-test of digital integrated circuits (IC). Existing parallel input methods of test stimuli can reduce test application times; however, they need to occupy multiple input ports. Thus, a novel method of test stimuli coding and data transmission was proposed to reduce the test application time of the test vectors and reduce the number of input ports required for the parallel input of test stimuli. This method was based on the segmentation of test stimuli. First, the test stimuli were evenly segmented into eight-bit wide. Second, the eight-bit data of each segment were encoded to the five-bit data according to the compatibility between the test data of each segment. The eight-bit test stimuli input can be completed in one or two clock cycles of automatic test equipment (ATE) by using the five input ports of the chip. The corresponding decoding circuit was added inside the netlist of the circuit to realize the rapid input of the test stimuli. Lastly, the ISCAS'89 benchmark circuit was used to conduct experiments, results of this coding method were then compared with those of the serial input method. Results show that the encoding method proposed in this study can save an average of 37% of the parallel input data width and 81.7% of the test stimuli input time. The proposed method in this study can also reduce the test application time and the cost of the IC test. The findings of this study can provide guidance for improving the scan testing method of digital IC.

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Test scheduling of System-on-Chip using Dragonfly and Ant Lion optimization algorithms

Chandrasekaran

Karthikeyan

Kumar

et al. 2021

IFS

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Test scheduling of System-on-Chip (SoC) is a major problem solved by various optimization techniques to minimize the cost and testing time. In this paper, we propose the application of Dragonfly and Ant Lion Optimization algorithms to minimize the test cost and test time of SoC. The swarm behavior of dragonfly and hunting behavior of Ant Lion optimization methods are used to optimize the scheduling time in the benchmark circuits. The proposed algorithms are tested on p22810 and d695 ITC’02 SoC benchmark circuits. The results of the proposed algorithms are compared with other algorithms like Ant Colony Optimization, Modified Ant Colony Optimization, Artificial Bee Colony, Modified Artificial Bee Colony, Firefly, Modified Firefly, and BAT algorithms to highlight the benefits of test time minimization. It is observed that the test time obtained for Dragonfly and Ant Lion optimization algorithms is 0.013188 Sec for D695, 0.013515 Sec for P22810, and 0.013432 Sec for D695, 0.013711 Sec for P22810 respectively with TAM Width of 64, which is less as compared to the other well-known optimization algorithms.

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A novel test data compression approach based on bit reversion

Cited by 3 publications

References 15 publications

New scan compression approach to reduce the test data volume

New scan compression approach to reduce the test data volume

Test Stimuli Segmentation and Coding Method

Test scheduling of System-on-Chip using Dragonfly and Ant Lion optimization algorithms

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