Efficient relocation of variable-sized hardware tasks for FPGA-based adaptive systems

Abstract

Adaptive systems based on FPGA architectures can benefit greatly from the high degree of flexibility offered by Dynamic partial reconfiguration (DPR). Thanks to DPR, hardware tasks composing an adaptive system can be allocated and relocated on demand or depending on the dynamically changing environment. The limitations in the existing tools provided by major FPGA manufacturers do not allow an efficient placement and relocation of variable-sized hardware tasks. This paper presents a design method for relocation of variable-sized hardware task on SRAM-based FPGAs for adaptive systems using dynamic partial reconfiguration (DPR). The proposed relocation procedure takes into account the communication between different reconfigurable regions and static region. This work gives a detailed description of the proposed partial bitsream relocation of variable-sized hardware tasks targeting the Virtex-5 FPGAs.