RePaBit: Automated generation of relocatable partial bitstreams for Xilinx Zynq FPGAs

Rettkowski, Jens; Friesen, Konstantin; Göhringer, Diana

doi:10.1109/reconfig.2016.7857186

Cited by 15 publications

(9 citation statements)

References 12 publications

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“…In [5], the authors proposed a framework to design DPR systems from a high-level unified modeling language (UML), while in [6] the authors create a custom modeling language to convert a Vivado HLS description of a system into a DPR implementation. Several researchers have also proposed design methodologies relying on bitstreams relocation [8,11,22]. Such approaches may offer some advantages in terms of flexibility.…”

Section: Discussionmentioning

confidence: 99%

Automating the design flow under dynamic partial reconfiguration for hardware-software co-design in FPGA SoC

Seyoum¹,

Pagani²,

Biondi³

et al. 2021

Proceedings of the 36th Annual ACM Symposium on Applied Computing

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Despite its benefits, hardware acceleration under dynamic partial reconfiguration (DPR) has not been fully leveraged by many system designers, mostly due to the complexities of the DPR design flow and the lack of efficient design tools to automate the design process. Furthermore, making such a design approach suitable for real-time embedded systems requires the need for extending the standard DPR design flow with additional design steps, which have to accurately account for the timing behavior of the software and hardware components of the design, as well as of the components of the computing platform (e.g., the reconfiguration interface).To address this problem, this paper presents DART, a tool that fully automates the design flow in a real-time DPR-based system that comprises both software and hardware components. The tool targets the Zynq 7-series and Ultrascale+ FPGA-based SoCs by Xilinx. It aims at alleviating the manual effort required by state-ofthe-art tools while not expecting high expertise in the design of programmable logic components under DPR. To this purpose, it fully automates the partitioning, floorplanning, and implementation (routing and bitstream generation) phases, generating a set of bitstreams starting from a set of tasks annotated with high-level timing requirements. The tool leverages mathematical optimization to solve the partitioning and floorplanning problems, and relies on a set of auto-generated scripts that interact with the vendor tools to mobilize the synthesis and implementation stages. DART has been experimentally evaluated with a case study application from an accelerated image processing system.

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Section: Discussionmentioning

confidence: 99%

Automating the design flow under dynamic partial reconfiguration for hardware-software co-design in FPGA SoC

Seyoum¹,

Pagani²,

Biondi³

et al. 2021

Proceedings of the 36th Annual ACM Symposium on Applied Computing

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“…Table 3 presents a comparison between Xilinx and Intel commercial reconfiguration flows and the main academic tools that can be used in Vivado to enhance Xilinx reconfiguration flow. Most academic tools enhance Vivado reconfiguration flow in only one facet such as relocation (e.g., RePaBit [25], Reloc [26] and the work of Oohmen et al [27]), or implementing flexible VA configuration styles (e.g., Amorphous DPR [28]). However, some of the aforementioned tools use bus macros or proxy logic to implement the interfaces; Thus, adding resource and timing overhead to the interfaces.…”

Section: A Coarse Granularitymentioning

confidence: 99%

An Integrated Approach and Tool Support for the Design of FPGA-Based Multi-Grain Reconfigurable Systems

et al. 2020

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Dynamic partial reconfiguration technique can be used to modify regions of an FPGA as large as the whole reconfigurable fabric or as small as individual logic elements. However, FPGA manufacturers have focused their efforts on designing tools that support the design of monolithic reconfigurable accelerators spanning large regions of the device. Nevertheless, in some applications, it is enough to fine-tune the accelerators' behavior instead of changing them entirely. In these cases, rather than allocating new accelerators, it is possible to reconfigure individual logic elements of the circuit, such as look-up tables or flip-flops. There is also an intermediate approach that targets the reconfigurability of accelerators composed of several tightly interconnected modules, such as overlays. In those architectures, it is possible to reconfigure only the modules that differ between the existing accelerator versions, thus reducing the reconfigurable footprint granularity. This paper proposes a classification of the approaches above, categorizing them as coarse, fine, and medium grain, respectively. There are neither commercial nor academic tools supporting multi-grain reconfiguration to take advantage of each granularity strength on commercial FPGAs. Differently, this paper proposes a tool called IMPRESS, that provides design-time and run-time support for multi-grain reconfiguration in Xilinx 7 Series FPGAs. Specific criteria are provided to combine the different granularity levels, trading off the benefits in terms of flexibility and performance, with different design and run-time costs. Two use cases in the image processing and neural network domains have been implemented to show how IMPRESS can build multi-grain reconfigurable systems.

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“…Different tools have been proposed in the last years targeting the design of relocatable DPR systems [1][2][3][4][5][6][7][8][9]. The most significant ones are analyzed in this section.…”

Section: State Of the Artmentioning

confidence: 99%

“…To the best of the author's knowledge, the most comprehensible tool for implementing DPR systems under Vivado is RePaBit, developed by J. Rettkowski et al [9]. It uses both the partial reconfiguration flow (PRF) [13] and Xilinx isolation design flow (IDF) [14] to ensure isolation between the static and the reconfigurable regions.…”

Section: State Of the Artmentioning

confidence: 99%

IMPRESS: Automated Tool for the Implementation of Highly Flexible Partial Reconfigurable Systems with Xilinx Vivado

Zamacola

Martínez

Mora

et al. 2018

2018 International Conference on ReConFigurable Computing and FPGAs (ReConFig)

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Dynamic partial reconfiguration is considered a great technique to increase flexibility in FPGA designs. However, partial reconfiguration flows supported by commercial tools, such as Xilinx Vivado, still have many limitations. Foremost among them are the lack of support for relocation, which leads to an increase in the on-system memory requirements and the synthesis time, as well as a reduced flexibility when it comes to the definition of reconfigurable regions. Several academic tools have appeared over the years to improve commercial flows. However, the technology shift from ISE to Vivado has left most of these tools unusable for newer FPGAs, including most of the Xilinx Series-7 devices. In this paper, authors present IMPRESS, a TCL scriptbased tool for the automated generation of relocatable partial bitstreams under Vivado, with a strong focus on the ease of use and the system flexibility. Special support is provided for the implementation of reconfigurable systems that include IP blocks generated with Vivado HLS and standardized bus interfaces. A stream-based reconfigurable architecture for image filtering, implemented in a fully automated manner on a Zynq SoPC, is provided as a use case of the tool.

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RePaBit: Automated generation of relocatable partial bitstreams for Xilinx Zynq FPGAs

Cited by 15 publications

References 12 publications

Automating the design flow under dynamic partial reconfiguration for hardware-software co-design in FPGA SoC

Automating the design flow under dynamic partial reconfiguration for hardware-software co-design in FPGA SoC

An Integrated Approach and Tool Support for the Design of FPGA-Based Multi-Grain Reconfigurable Systems

IMPRESS: Automated Tool for the Implementation of Highly Flexible Partial Reconfigurable Systems with Xilinx Vivado

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