IMPRESS: Automated Tool for the Implementation of Highly Flexible Partial Reconfigurable Systems with Xilinx Vivado

Abstract

Dynamic partial reconfiguration is considered a great technique to increase flexibility in FPGA designs. However, partial reconfiguration flows supported by commercial tools, such as Xilinx Vivado, still have many limitations. Foremost among them are the lack of support for relocation, which leads to an increase in the on-system memory requirements and the synthesis time, as well as a reduced flexibility when it comes to the definition of reconfigurable regions. Several academic tools have appeared over the years to improve commercial flows. However, the technology shift from ISE to Vivado has left most of these tools unusable for newer FPGAs, including most of the Xilinx Series-7 devices. In this paper, authors present IMPRESS, a TCL scriptbased tool for the automated generation of relocatable partial bitstreams under Vivado, with a strong focus on the ease of use and the system flexibility. Special support is provided for the implementation of reconfigurable systems that include IP blocks generated with Vivado HLS and standardized bus interfaces. A stream-based reconfigurable architecture for image filtering, implemented in a fully automated manner on a Zynq SoPC, is provided as a use case of the tool.

Automating the design flow under dynamic partial reconfiguration for hardware-software co-design in FPGA SoC

“…In [5], the authors proposed a framework to design DPR systems from a high-level unified modeling language (UML), while in [6] the authors create a custom modeling language to convert a Vivado HLS description of a system into a DPR implementation. Several researchers have also proposed design methodologies relying on bitstreams relocation [8,11,22]. Such approaches may offer some advantages in terms of flexibility.…”

An Integrated Approach and Tool Support for the Design of FPGA-Based Multi-Grain Reconfigurable Systems

“…However, in slot/grid VAs, where RMs can be arranged in different positions and interconnections are highly flexible, it is the user's responsibility to ensure that an RMs is compatible with other RMs and the static system, as it would be computationally expensive to check at runtime that interfaces are compatible. The downside of using relocation is that due to the extra design constraints (e.g., same interfaces and blocker net) the maximum frequency of the system can diminish, as already shown in [11].…”

“…is an open-source tool for implementing multi-grain reconfigurable systems [46]. It was proposed initially in [11] for designing reconfigurable systems using flexible VAs and relocatable reconfigurable modules. In this work, IMPRESS has been extended to support multi-grain reconfiguration.…”

“…For that reason, it is not possible to compare the implementation time of both reconfiguration flows. We refer the reader to the original paper of IMPRESS [11] that compared the implementation time to build an image filter architecture using an island VA with IMPRESS and with Xilinx reconfiguration flow. In the case of Xilinx reconfiguration flow it took 131 seconds to implement the static system and 100 seconds to implement each RM.…”

“…This paper provides an integrated vision of multi-grain reconfiguration, showing how coarse, medium, and fine grain reconfiguration can be combined in a given design to leverage each granularity strength. Moreover, we have extended the IMPRESS design automation tool, initially proposed in [11] and [12], with support for design and run-time management of medium grain and fine grain reconfiguration. With IMPRESS, it is now possible to combine all the three granularities in the same system.…”