Relocatable Partial Bitstreams For Virtual Overlay Architectures atop Field-Programmable Gate Arrays

Mudza, Zbigniew

doi:10.23919/mixdes49814.2020.9155790

Cited by 2 publications

(3 citation statements)

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“…Its distinctive features are: This study focuses on different aspects of Virtual CGRA implementation in FPGAs; partition relocatability is only presented to the extent required to comprehend the proposed solutions. Technical details of all methods and tools used to obtain reconfigurable module relocatability are described in full in a previous publication by the main author [29,39].…”

Section: Relocatable Partitions In Fpgasmentioning

confidence: 99%

“…Although Xilinx Vivado toolchain offers no support for module relocation per se, it can be obtained using a combination of inbuilt Partial Reconfiguration Flow (PRF) and Isolation Design Flow (IDF) with additional constraining and TCL scripted processing of intermediate results. The techniques used to provide module relocatability are described in detail in previous work by the main author of this article [29,39]. General concept and details with crucial influence on floorplanning are outlined below.…”

Section: Module Relocationmentioning

confidence: 99%

“…Then, it attempts to find optimal locations for individual partitions in a reasonably short time. The obtained floorplan is then used to implement the design using Xilinx Vivado toolset and module relocation methodology [29,39]. The same parametric static overlay can be implemented with different floorplans using various PBlock constructions and PE array sizes or targeting different FPGA.…”

Section: Design Flowmentioning

confidence: 99%

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Mapping Processing Elements of Custom Virtual CGRAs onto Reconfigurable Partitions

Mudza

Kiełbik

2022

Electronics

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FPGAs can provide application-specific acceleration for computationally demanding tasks. However, they are rarely considered general-purpose platforms due to low productivity of software development and long reconfiguration time. These problems can be mitigated by implementing a coarser overlay atop the FPGA fabric. Combining this approach with partial reconfiguration allows for the modification of individual processing elements (PEs) of the virtual architecture without altering the rest of the system. Module relocation can be used to share implementation details between functionally equivalent PEs that use identical sets of resources, thus eliminating redundant placement and routing runs. Proper floorplanning is crucial for virtual Coarse-Grained Reconfigurable Architectures (CGRAs) with relocatable PEs considering their tendency to use nearest-neighbor connection patterns. It requires solving two problems—finding identical regions in the FPGA fabric and assigning individual partitions to certain locations. This article presents minor improvements of a state-of-the-art solution for the first and proposes a novel technique for solving the other. The proposed automated floorplanner uses modified breadth-first search with direction-based penalties to create initial floorplan consistent with geometry of logical array, then improves the result with 2-opt local optimization. Compared to simulated annealing solutions, the proposed approach allows for the reduction in the floorplanning time by two to three orders of magnitude without compromising the quality of the results.

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Section: Relocatable Partitions In Fpgasmentioning

confidence: 99%

Section: Module Relocationmentioning

confidence: 99%

Section: Design Flowmentioning

confidence: 99%

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