Efficient and High-Throughput Implementations of AES-GCM on FPGAs

Zhou, Gang; Michalik, H.; Hinsenkamp, L.

doi:10.1109/fpt.2007.4439248

Cited by 34 publications

(35 citation statements)

References 7 publications

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“…The performance of our previous architecture [6] is limited because a new reconfiguration is needed in case of changing the key. Also, Zhou et al [8] claimed a throughput improvement to their previous KOA-based GHASH [7] by using pipelined KOA, but we discussed how their method is not efficient for throughput improvement as shown in Eq. 11.…”

Section: Efficient Koa-based Ghashmentioning

confidence: 95%

“…Four different architectures of FPGAs-based AES-GCM have been presented in the open literature [6][7][8][9]. It is clear that these contributions do generally have different challenges related to the performance of their architectures.…”

Section: Efficient Koa-based Ghashmentioning

confidence: 98%

“…KOA was used by [7] to reduce the complexity (consumed area) of the GF(2 128 ) multiplier as shown in Fig. 3a.…”

Section: Hardware Implementationmentioning

confidence: 99%

“…The drawback of the architecture presented in [7] is the the critical delay resulting from the multiplication stage. In order to reduce the data path (critical delay) of the KOA multiplier, pipelining concept was accomplished by [8] as shown in Fig.…”

Section: Hardware Implementationmentioning

confidence: 99%

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AES-GCM and AEGIS: Efficient and High Speed Hardware Implementations

Abdellatif

Chotin-Avot

Mehrez

2016

J Sign Process Syst

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Authenticated Encryption (AE) is a block cipher mode of operation which provides confidentiality and integrity simultaneously. In terms of the hardware implementation, it produces smaller area compared to two separated algorithms. Therefore, it has become popular and a number of modes have been proposed. This paper presents two efficient hardware implementations for AE schemes, AES-GCM and AEGIS. In terms of AES-GCM, the performance of the system is always determined by the Galois Hash (GHASH) architecture because of the inherent computation feedback. This paper introduces an efficient method for implementing the pipelined Karatsuba Ofman Algorithm (KOA)-based GHASH on FPGAs. In particular, the computation feedback is removed by analyzing the complexity of the computation process. In addition, an efficient AEGIS is also implemented using only five AES rounds. The proposed architectures are evaluated with three different implementations of AES SubBytes (BRAMs-based SubBytes, composite field-based SubBytes, and LUT-based SubBytes) to increase the flexibility of the presented work. The presented architectures are implemented using Xilinx Virtex-5 FPGAs. Our comparison to previous work reveals that our architectures are more performance-efficient (Throughput/Slices).

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Section: Efficient Koa-based Ghashmentioning

confidence: 95%

Section: Efficient Koa-based Ghashmentioning

confidence: 98%

“…KOA was used by [7] to reduce the complexity (consumed area) of the GF(2 128 ) multiplier as shown in Fig. 3a.…”

Section: Hardware Implementationmentioning

confidence: 99%

Section: Hardware Implementationmentioning

confidence: 99%

See 2 more Smart Citations

AES-GCM and AEGIS: Efficient and High Speed Hardware Implementations

Abdellatif

Chotin-Avot

Mehrez

2016

J Sign Process Syst

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“…Hodjat et al [8] report an AES-128 implementation with 21.54 Gbit/s throughput using 5,177 "slices" and 84 BRAMs on a Xilinx Virtex-II Pro 20(-7) FPGA. Zhou et al [19] recently reported figures for an AES implementation of the Galois Counter Mode (GCM) on a Xilinx Virtex-4 LX40(-12) FPGA achieving a throughput of 20.6 Gbit/s without use of BRAMs, which uses 8,035 "slices". Gaj and Chodowiec [6] proposed an area-efficient AES implementation on a Xilinx Spartan-II 30(-6) with 222 "slices" and 3 BlockRAMs with an encryption rate of 0.166 Gbit/s.…”

Section: Prior Workmentioning

confidence: 99%

DSPs, BRAMs and a Pinch of Logic: New Recipes for AES on FPGAs

Drimer

Güneysu

Paar

2008

2008 16th International Symposium on Field-Programmable Custom Computing Machines

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We present an AES cipher implementation that is based on the BlockRAM and DSP units embedded within FPGAs. An iterative "basic" module outputs a 32 bit column of an AES round each clock cycle, with a throughput of 1.76 Gbit/s when processing two 128 bit inputs. This construct is replicated four times for a 128 bit datapath for a full AES round with 6.21 Gbit/s throughput when processing eight inputs. Finally, the "round" module is replicated ten times for a fully unrolled design that yields over 55 Gbit/s of throughput. The combination and arrangement of the specialized embedded functions available in the FPGA allows us to implement our designs using very few traditional user logic elements such as flip-flops and lookup tables, yet still achieve these high throughputs. The complete source code for these designs is made publicly available for use in further research and for replicating our results. Our contribution ends with a discussion of comparing cipher implementations in the literature, and why these comparisons can be meaningless without a common reporting style, platform, or within the context of a specific constrained application.

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A novel high speed Artificial Neural Network–based chaotic True Random Number Generator on Field Programmable Gate Array

Alçın

Koyuncu

Tuna

et al. 2018

Circuit Theory & Apps

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Summary It is well observed that cryptographic applications have great challenges in guaranteeing high security as well as high throughput. Artificial neural network (ANN)–based chaotic true random number generator (TRNG) structure has not been unprecedented in current literature. This paper provides a novel type of high‐speed TRNG based on chaos and ANN implemented in a Xilinx field‐programmable gate array (FPGA) chip. The paper consists of two main parts. In the first part, chaos analyses of Pehlivan‐Uyaroglu_2010 chaotic system (PUCS) have been accomplished to prove that PUCS operates in chaotic regime. So PUCS can be an efficient alternative to the entropy source for classical TRNGs. In the second part, the hardware design of the proposed TRNG has been created using VHDL in Xilinx platform. As a result, the implemented TRNG offers throughput up to 115.794 Mbps. Besides, the generated random numbers have been tested with the FIPS 140‐1 and NIST 800.22 test suites. The high quality of generated true random numbers have been confirmed by passing all randomness tests. The results have shown that the proposed system can provide not only high throughput but also high quality random bit sequences for a wide variety of embedded cryptographic applications.

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Efficient and High-Throughput Implementations of AES-GCM on FPGAs

Cited by 34 publications

References 7 publications

AES-GCM and AEGIS: Efficient and High Speed Hardware Implementations

AES-GCM and AEGIS: Efficient and High Speed Hardware Implementations

DSPs, BRAMs and a Pinch of Logic: New Recipes for AES on FPGAs

A novel high speed Artificial Neural Network–based chaotic True Random Number Generator on Field Programmable Gate Array

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