DSPs, BRAMs and a Pinch of Logic: New Recipes for AES on FPGAs

Abstract

We present an AES cipher implementation that is based on the BlockRAM and DSP units embedded within FPGAs. An iterative "basic" module outputs a 32 bit column of an AES round each clock cycle, with a throughput of 1.76 Gbit/s when processing two 128 bit inputs. This construct is replicated four times for a 128 bit datapath for a full AES round with 6.21 Gbit/s throughput when processing eight inputs. Finally, the "round" module is replicated ten times for a fully unrolled design that yields over 55 Gbit/s of throughput. The combination and arrangement of the specialized embedded functions available in the FPGA allows us to implement our designs using very few traditional user logic elements such as flip-flops and lookup tables, yet still achieve these high throughputs. The complete source code for these designs is made publicly available for use in further research and for replicating our results. Our contribution ends with a discussion of comparing cipher implementations in the literature, and why these comparisons can be meaningless without a common reporting style, platform, or within the context of a specific constrained application.

A Pay-per-Use Licensing Scheme for Hardware IP Cores in Recent SRAM-Based FPGAs

“…The main concepts which enable the proposed scheme are the use of a trusted third party to provide an independent metering service between IP providers, system developers and customers, and the use of the self-reconfiguring techniques of modern FPGA devices to enhance the FPGA's protection primitives. Similar protocols based on these 1556-6013/$26.00 © 2011 IEEE techniques have been proposed earlier [1], [2], but we specifically aim for a scheme which is more practical and can be deployed on currently existing devices. Moreover, our proposal allows us to enforce a "pay-per-use" licensing scheme where system developers pay a small amount to the IP provider in order to use a particular module only once, instead of a large sum to use it indefinitely.…”

“…2 2) The Core Vendor (CV): offers access to its soft IP cores, i.e., innovative logical circuits for configuration on FPGAs, by licensing other parties to use them. We focus on pay-per-use licensing schemes with technical enforcement measures.…”

Security evaluation of different AES implementations against practical setup time violation attacks in FPGAs

“…As compared to other architectures we found that sbox in LUT proves to be most robust implementation. We make an attempt to relate our scenario with what has been published elsewhere [11], [20]. In terms of cost, the sbox in LUT consumes the maximum area followed by sbox inGF(2 4 ) and RAM respectively.…”

“…A sbox which gets faulty at lower voltage is more secure because it is more likely that some other part of the design stops working at lower voltages. Recently, few methods have been reported [20] which suggest to synthesize the bulky parts of AES like SubBytes & MixColumns into the peripherals like block RAM, DSPs etc. These methods reduce the logic utilization in the FPGA and hence are cost effective.…”

A Protocol for Secure Remote Updates of FPGA Configurations

“…The design and presentation of our protocol was influenced by our experience with an ongoing logic-circuit implementation on a Virtex-5 evaluation board, using the publicly available AES design by Drimer et al [12].…”