Security evaluation of different AES implementations against practical setup time violation attacks in FPGAs

Bhasin, Shivam; Selmane, Nidhal; Guilley, Sylvain; Danger, Jean‐Luc

doi:10.1109/hst.2009.5225057

Cited by 20 publications

(9 citation statements)

References 13 publications

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“…Note that this work is independent of the encryption algorithm. We do not demonstrate an attack on AES specifically, it has been well covered elsewhere [4], [7], [23], [34]. Our proposal is generic and can be applied to any sort of code, depending on the presence of the basic set of assembly instructions required (see Section 3).…”

Section: Resultsmentioning

confidence: 99%

NOP-Oriented Programming: Should we Care?

Péneau

Claudepierre

Hardy

et al. 2020

2020 IEEE European Symposium on Security and Privacy Workshops (EuroS&PW)

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Many fault injection techniques have been proposed in the recent years to attack computing systems, as well as the corresponding countermeasures. Most of published attacks are limited to one or a few faults. We provide a theoretical analysis of instruction skip attacks to show how an attacker can modify an application behavior at run-time when thousands of instruction skips are possible. Our main result is that instruction skip is Turing-complete under our theoretical model while requiring the presence of only common instructions in the binary. As a consequence, we show that current software-based countermeasures are fragile. In addition, we release a modification of gem5 that implements a classical instruction skip fault model that we used for our experiments. We believe this kind of simulation tools are useful to help the community explore attacks and hardware and software countermeasures.

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Section: Resultsmentioning

confidence: 99%

NOP-Oriented Programming: Should we Care?

Péneau

Claudepierre

Hardy

et al. 2020

2020 IEEE European Symposium on Security and Privacy Workshops (EuroS&PW)

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“…We find that stressing the operating frequency leads to appearance of faults in intermediate key values and hence an incorrect ciphertext. In literature, there exist many ways of stress injections like optical fault injections [15] and voltage reduction or underpowering the circuit [16] but in this article we subject the AES-core to stress injection through high transient frequencies which induce fault in the FPGA implementation of key schedule of the 32-bit architecture of the AES-core.…”

Section: Investigation Of Practical Fault Modelmentioning

confidence: 99%

A Fault Analysis Perspective for Testing of Secured SoC Cores

Ali¹,

Mazumdar

Mukhopadhyay

2013

IEEE Des. Test

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h WITH THE GROWING importance of secured communication the importance of cryptographic cores have increased. Hardware solutions of these cores are developed using application specific integrated circuit (ASIC) libraries or on field programmable gate array (FPGA) platforms. Recently, the enhancement of the FPGAs has lead to the use of these platforms for in-house development of cryptographic IPs. The fact that the entire design can be performed in the laboratory, without relying on an untrusted third party fab makes such design flows ideal from the point of view of security [1].In a system-on-chip (SoC) the cores are pretested and preverified. However the test and verification is mostly functional and the integrator is satisfied if the core meets its functionalities. However for cryptographic cores, apart from the normal functionality it is also important to model the core under not normal conditions. A related study of cryptographic algorithms and the designs thereof is known as differential fault analysis (DFA) [2]. This analysis technique investigates the nature of induced faults when a device is stressed beyond its normal operating conditions. While the core integrator is mostly satisfied when the faults are not permanent, for the attacker a single transient fault is enough to get the complete key for even standard ciphers like AES-128 [3].Most of the attacks exploiting the faults on AES target the AES data-path and assume byte faults. Hence researchers have tried to apply classical fault tolerance techniques like parity, invariance, hardware and time redundancy [4], [5] to detect these faults in the data-path of AES [6]. However there are other DFAs on AES which target the key-schedule. Faults can be injected in the round keys either by corrupting the key scheduling process (on the fly round key generation) or corrupting the memory (precomputation process) where the round keys are preloaded. Such faults will not be detected by the countermeasures which only protect the AES data path. DFA on AES key schedule [7], [8], was considered more difficult than attacking AES states as it required more number of faulty ciphertexts. Recently a DFA on AES-128 key schedule was proposed [9], which required only one pair of fault free and faulty ciphertexts. The most efficient DFA on key schedule [8] required three to four pairs and four pairs of fault free and faulty ciphertexts, respectively. However, all these attacks exploit single byte faults. Researchers show that while there are several inexpensive techniques for fault injection [10]Editor's notes: Can the inputs of a cryptocore be stressed to leak the secret key? This article demonstrates such a vulnerability challenging secure integration of these cores in a system-on-chip design.VSwarup Bhunia, Case Western Reserve University

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“…Underfeeding, clock glitches and Electromagnetic fault injection (EMFI) rely on the same fault mechanism, timing violation. In [3], the authors characterize this mechanism on a FPGA with underfeeding.…”

Section: Previous Workmentioning

confidence: 99%

Let's shock our IoT's heart

Bukasa

Lashermes

Lanet

et al. 2018

Proceedings of the 13th International Conference on Availability, Reliability and Security

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A fault attack is a well-known technique where the behaviour of a chip is voluntarily disturbed by hardware means in order to undermine the security of the information handled by the target. In this paper, we explore how Electromagnetic fault injection (EMFI) can be used to create vulnerabilities in sound software, targeting a Cortex-M3 microcontroller. Several use-cases are shown experimentally: control flow hijacking, buffer overflow (even with the presence of a canary), covert backdoor insertion and Return Oriented Programming can be achieved even if programs are not vulnerable in a software point of view. These results suggest that the protection of any software against vulnerabilities must take hardware into account as well.

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Security evaluation of different AES implementations against practical setup time violation attacks in FPGAs

Cited by 20 publications

References 13 publications

NOP-Oriented Programming: Should we Care?

NOP-Oriented Programming: Should we Care?

A Fault Analysis Perspective for Testing of Secured SoC Cores

Let's shock our IoT's heart

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