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2016
DOI: 10.1007/s11265-016-1104-y
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AES-GCM and AEGIS: Efficient and High Speed Hardware Implementations

Abstract: Authenticated Encryption (AE) is a block cipher mode of operation which provides confidentiality and integrity simultaneously. In terms of the hardware implementation, it produces smaller area compared to two separated algorithms. Therefore, it has become popular and a number of modes have been proposed. This paper presents two efficient hardware implementations for AE schemes, AES-GCM and AEGIS. In terms of AES-GCM, the performance of the system is always determined by the Galois Hash (GHASH) architecture bec… Show more

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Cited by 11 publications
(2 citation statements)
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“…The round function of each round of the AES algorithm must go through the process of byte substitution, row shift, column mixing transformation, and round key addition operation. Compared with other algorithms, the AES algorithm is more symmetrical, and the expression is simple and easy to understand [23]. Byte substitution is the only nonlinear transformation in the algorithm.…”
Section: Mobile Iot Information Security Encryption Algorithmmentioning
confidence: 99%
“…The round function of each round of the AES algorithm must go through the process of byte substitution, row shift, column mixing transformation, and round key addition operation. Compared with other algorithms, the AES algorithm is more symmetrical, and the expression is simple and easy to understand [23]. Byte substitution is the only nonlinear transformation in the algorithm.…”
Section: Mobile Iot Information Security Encryption Algorithmmentioning
confidence: 99%
“…L. Henzen et al [54] have presented his 100 Gbps implementation of the AES-GCM algorithm for Ethernet application on Xilinx Virtex 5 FPGA. K. M. Abdellatif et al [55], [56] has shown his high-speed implementation for slow-changing key application and AEGIS algorithm using Xilinx Virtex 5 FPGA. Besides, Y. Zhang et al [52] have presented the high throughput implementation of the AES-GCM algorithm using pipeline architecture on Xilinx Virtex-5 FPGA.…”
Section: B Comparison Of Proposed Workmentioning
confidence: 99%