A novel high speed Artificial Neural Network–based chaotic True Random Number Generator on Field Programmable Gate Array

Abstract

Summary It is well observed that cryptographic applications have great challenges in guaranteeing high security as well as high throughput. Artificial neural network (ANN)–based chaotic true random number generator (TRNG) structure has not been unprecedented in current literature. This paper provides a novel type of high‐speed TRNG based on chaos and ANN implemented in a Xilinx field‐programmable gate array (FPGA) chip. The paper consists of two main parts. In the first part, chaos analyses of Pehlivan‐Uyaroglu_2010 chaotic system (PUCS) have been accomplished to prove that PUCS operates in chaotic regime. So PUCS can be an efficient alternative to the entropy source for classical TRNGs. In the second part, the hardware design of the proposed TRNG has been created using VHDL in Xilinx platform. As a result, the implemented TRNG offers throughput up to 115.794 Mbps. Besides, the generated random numbers have been tested with the FIPS 140‐1 and NIST 800.22 test suites. The high quality of generated true random numbers have been confirmed by passing all randomness tests. The results have shown that the proposed system can provide not only high throughput but also high quality random bit sequences for a wide variety of embedded cryptographic applications.

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“…In [11], performance differences between the conventional TRNG method that used a chaotic system and recently designed FPGA-based chaotic systems have been compared. In [12], the authors proposed a novel type of high-speed TRNG based on chaos and ANN implemented in an FPGA chip. The generated random numbers have been tested with the NIST 800.22 and FIPS 140-1 test suites.…”

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“…Alcin et al proposed a high-speed chaotic true random number generator based on artificial neural network. They claimed that it generates random numbers that pass all randomness tests and this TRNG can be used in cryptographic and communication applications [28].…”

Tunnel FET‐based ultralow‐power and hardware‐secure circuit design considering p‐i‐n forward leakage

“…Meanwhile, the globalization of IC design and manufacturing introduces hardware security threats such as hardware trojans, side‐channel analysis, and IC reverse engineering (RE) . Hardware‐oriented security offers new Compementary metal‐oxide semiconductor (CMOS)‐based security primitives like true random number generators (TRNGs), physically unclonable functions, and other circuit design methodologies to make systems robust against security attacks . However, CMOS‐based security primitives consume high power and area and require additional source/drain doping variations to create stealthy manipulations for obfuscation .…”

“…[19][20][21] Hardware-oriented security offers new Compementary metal-oxide semiconductor (CMOS)-based security primitives like true random number generators (TRNGs), physically unclonable functions, and other circuit design methodologies to make systems robust against security attacks. [22][23][24] However, CMOS-based security primitives consume high power and area and require additional source/drain doping variations to create stealthy manipulations for obfuscation. [25][26][27] To overcome the limitations of CMOS, emerging devices are investigated by leveraging their inherent unique characteristics for hardware security.…”