Efficient Analog CAM Design

Jinane, Bazzi,; Sweidan, Jana; Fouda, Mohammed E.; Kanj, Rouwaida

doi:10.48550/arxiv.2203.02500

Cited by 4 publications

(6 citation statements)

References 15 publications

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“…Multi-bit CAM Cell: Recent works show the ability to fabricate multi-bit cells enabling much denser associative memories [26], [51], [53]. Hence, finding ways to handle multi-bit devices and extending the functionality to multivalued logic is of interest.…”

Section: Discussionmentioning

confidence: 99%

In-Memory Associative Processors: Tutorial, Potential, and Challenges

Fouda

Yantır

Eltawil

et al. 2022

IEEE Trans. Circuits Syst. II

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In-memory computing is an emerging computing paradigm that overcomes the limitations of exiting Von-Neumann computing architectures such as the memory-wall bottleneck. In such paradigm, the computations are performed directly on the data stored in the memory, which highly reduces the memory-processor communications during computation. Hence, significant speedup and energy savings could be achieved especially with data-intensive applications. Associative processors (APs) were proposed in the seventies and recently were revived thanks to the high-density memories. In this tutorial brief, we overview the functionalities and recent trends of APs in addition to the implementation of each content-addressable memory with different technologies. The AP operations and runtime complexity are also summarized. We also explain and explore the possible applications that can benefit from APs. Finally, the AP limitations, challenges, and future directions are discussed.

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Section: Discussionmentioning

confidence: 99%

In-Memory Associative Processors: Tutorial, Potential, and Challenges

Fouda

Yantır

Eltawil

et al. 2022

IEEE Trans. Circuits Syst. II

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“…Compared to other SOTA hardware accelerators, DT2CAM achieves the lowest energy, highest throughput, lowest area overhead, and lowest FOM (preferred). It is also worth mentioning that our framework, including selective precharge, can be extended to accommodate other ReRAM cell typologies, including ACAM [40], resulting in better performance which we consider for our future work.…”

Section: Discussionmentioning

confidence: 99%

DT2CAM: A Decision Tree to Content Addressable Memory Framework

Rakka¹,

Fouda²,

Kanj³

et al. 2022

Preprint

Self Cite

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Decision trees are considered one of the most powerful tools for data classification. Accelerating the decision tree search is crucial for on-the-edge applications that have limited power and latency budget. In this paper, we propose a Content Addressable Memory (CAM) Compiler for Decision Tree (DT) inference acceleration. We propose a novel "adaptiveprecision" scheme that results in a compact implementation and enables an efficient bijective mapping to Ternary Content Addressable Memories while maintaining high inference accuracies. In addition, a Resistive-CAM (ReCAM) functional synthesizer is developed for mapping the decision tree to the ReCAM and performing functional simulations for energy, latency, and accuracy evaluations. We study the decision tree accuracy under hardware non-idealities including device defects, manufacturing variability, and input encoding noise. We test our framework on various DT datasets including Give Me Some Credit, Titanic, and COVID-19. Our results reveal up to 42.4% energy savings and up to 17.8x better energy-delay-area product compared to the stateof-art hardware accelerators, and up to 333 million decisions per sec for the pipelined implementation.

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“…Several types of memristor-based aCAM have been proposed in the literature. In (Bazzi et al, 2022), the authors analyzed and compared different memristor-based aCAM cells. They found that the 8T2M cell was the most energy-efficient and offered low latency, low failure probability, and small area compared to other types of aCAMs.…”

Section: Acam Cellmentioning

confidence: 99%

Hardware acceleration of DNA pattern matching using analog resistive CAMs

Bazzi,

Sweidan,

Fouda

et al. 2024

Front.Electron.

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DNA pattern matching is essential for many widely used bioinformatics applications. Disease diagnosis is one of these applications since analyzing changes in DNA sequences can increase our understanding of possible genetic diseases. The remarkable growth in the size of DNA datasets has resulted in challenges in discovering DNA patterns efficiently in terms of run time and power consumption. In this paper, we propose an efficient pipelined hardware accelerator that determines the chance of the occurrence of repeat-expansion diseases using DNA pattern matching. The proposed design parallelizes the DNA pattern matching task using associative memory realized with analog content-addressable memory and implements an algorithm that returns the maximum number of consecutive occurrences of a specific pattern within a DNA sequence. We fully implement all the required hardware circuits with PTM 45-nm technology, and we evaluate the proposed architecture on a practical human DNA dataset. The results show that our design is energy-efficient and accelerates the DNA pattern matching task by more than 100× compared to the approaches described in the literature.

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Efficient Analog CAM Design

Cited by 4 publications

References 15 publications

In-Memory Associative Processors: Tutorial, Potential, and Challenges

In-Memory Associative Processors: Tutorial, Potential, and Challenges

DT2CAM: A Decision Tree to Content Addressable Memory Framework

Hardware acceleration of DNA pattern matching using analog resistive CAMs

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