Effects of Structural Properties of Hf-Based Gate Stack on Transistor Performance

Abstract

Electron traps in ALD and MOCVD HfO2 and HfSiO high-k dielectrics were investigated using both conventional DC and pulse measurements. It was found that the traps in the gate stack could be associated with defects of different activation energies and capture cross-sections. This points to potentially different origins of the electrically active defects, which can be either intrinsic or process-related. Structural non-uniformity of the high-k film, associated with grain formation and phase separation, may lead to variation of electrical properties of the gate dielectric along the transistor channel. Effects of such dielectric non-uniformity, as well as electron trapping, on the measured transistor mobility were evaluated.

On the scaling issues and high-κ replacement of ultrathin gate dielectrics for nanoscale MOS transistors

“…The hydrogen species will then diffuse away the interface at the elevated temperature and results in the threshold voltage shift [197]. Similar phenomenon is also observed in high-j gate dielectric [198][199][200] but the physical origins of the NBTI are much complicated. As mentioned earlier, high-j materials are often found to have higher bulk oxide trap and interface trap density.…”

“…It was found that the oxide trap and interface trap recoveries are about 40% and 25% respectively for HfSiON film [200]. It was also found that the higher initial trap density would lead to larger threshold voltage shift during the stressing [198]. This is an indirect evident for this conjecture.…”

The Pulsed Id-Vgmethodology and Its Application to the Electron Trapping Characterization of High-κ gate Dielectrics

“…As the interface becomes thinner, the difference between the pulsed and DC mobility for a given gate stack becomes greater. The overall degradation in the pulsed (intrinsic) mobility as the interface layer becomes thinner can be attributed to poorer interfacial layer quality [102] and greater effects of soft optical phonons [64] and crystallinity [21,103].…”

Intrinsic parameter fluctuations due to random grain orientations in high-κ gate stacks

“…1. Some of these factors [3] will also introduce intrinsic parameter fluctuations in the corresponding MOSFETs, similar to the fluctuations introduced by random discrete dopants and oxide thickness variations.…”