Effects of High-k Dielectrics with Metal Gate for Electrical Characteristics of SOI TRI-GATE FinFET Transistor

Rahou, Fatima Zohra; Bouazza, A. Guen; Bouazza, B.

doi:10.21272/jnep.8(4(1)).04037

Cited by 8 publications

(3 citation statements)

References 6 publications

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“…The same simulation was also performed on GaAs FinFET, and similarly, La 2 O 3 was capable of achieving the smallest DIBL (47 mV/V), lowest SS (76 mV/dec), and highest g m among all the gate dielectrics [149]. As for TG FinFET, simulation was carried out on SOI substrate by the SILVACO TCAD simulator with the device structure depicted in Figure 17d [150]. The L g , EOT, fin width and height, buried-oxide thickness, body, and source/drain doping concentrations are set as 30, 1.2, 10, 20 nm, 5 × 10 17 cm −3 , and 5 × 10 20 cm −3 , respectively.…”

Section: Other Novel Metal-oxide-semiconductor (Mos) Devicesmentioning

confidence: 99%

Advances in La-Based High-k Dielectrics for MOS Applications

2019

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This paper reviews the studies on La-based high-k dielectrics for metal-oxide-semiconductor (MOS) applications in recent years. According to the analyses of the physical and chemical characteristics of La2O3, its hygroscopicity and defects (oxygen vacancies, oxygen interstitials, interface states, and grain boundary states) are the main problems for high-performance devices. Reports show that post-deposition treatments (high temperature, laser), nitrogen incorporation and doping by other high-k material are capable of solving these problems. On the other hand, doping La into other high-k oxides can effectively passivate their oxygen vacancies and improve the threshold voltages of relevant MOS devices, thus improving the device performance. Investigations on MOS devices including non-volatile memory, MOS field-effect transistor, thin-film transistor, and novel devices (FinFET and nanowire-based transistor) suggest that La-based high-k dielectrics have high potential to fulfill the high-performance requirements in future MOS applications.

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Section: Other Novel Metal-oxide-semiconductor (Mos) Devicesmentioning

confidence: 99%

Advances in La-Based High-k Dielectrics for MOS Applications

2019

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“…HfO 2 is compatible with a silicon substrate and possesses a high dielectric constant (ε ≈ 25), a large bandgap (5.68 eV), band offsets with silicon, a low leakage current, and a lattice parameter that is close to that of silicon with a modest lattice misfit (ca. 5%) [ 11 ].…”

Section: Introductionmentioning

confidence: 99%

Reduced subthreshold swing in a vertical tunnel FET using a low-work-function live metal strip and a low-k material at the drain

Kanagarajan,

Sadhasivan

2024

Beilstein J. Nanotechnol.

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In this research paper, a vertical tunnel field-effect transistor (TFET) structure containing a live metal strip and a material with low dielectric constant is designed, and its performance metrics are analyzed in detail. Low-k SiO2 is incorporated in the channel–drain region. A live molybdenum metal strip with low work function is placed in a high-k HfO2 layer in the source–channel region. The device is examined by the parameters Ioff, subthreshold swing, threshold voltage, and Ion/Ioff ratio. The introduction of a live metal strip in the dielectric layer closer to the source–channel interface results in a minimum subthreshold slope and a good Ion/Ioff ratio. The low-k material at the drain reduces the gate-to-drain capacitance. Both the SiO2 layer and the live metal strip show excellent leakage current reduction to 1.4 × 10−17 A/μm. The design provides a subthreshold swing of 5 mV/decade, which is an excellent improvement in TFETs, an on-current of 1.00 × 10−5 A/μm, an Ion/Ioff ratio of 7.14 × 1011, and a threshold voltage of 0.28 V.

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“…Primary method to increase productivity and performance is scaling, But due to Short channel effects and junction leakage current with scaling, it is difficult to follow moore's law with bulk CMOS. So the need to SOI technology arises [17].…”

Section: Introductionmentioning

confidence: 99%

Comparison of Three Dimensional Partially and Fully Depleted SOI MOSFET Characteristics Using Mathcad

Goel¹,

Pandey²

2016

J. Nano- Electron. Phys.

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In this Paper, comparison of three Dimensional characteristics between partially and fully depleted Silicon-On-Insulator (SOI MOSFET) is presented, this is done through 3D device modeling using mathcad, based on the numerical solution of three dimensional Poisson's equation. Behavior of Various Parameters like Surface Potential, Threshold Voltage, Electric field and Drain current are presented in this paper.

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Effects of High-k Dielectrics with Metal Gate for Electrical Characteristics of SOI TRI-GATE FinFET Transistor

Cited by 8 publications

References 6 publications

Advances in La-Based High-k Dielectrics for MOS Applications

Advances in La-Based High-k Dielectrics for MOS Applications

Reduced subthreshold swing in a vertical tunnel FET using a low-work-function live metal strip and a low-k material at the drain

Comparison of Three Dimensional Partially and Fully Depleted SOI MOSFET Characteristics Using Mathcad

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