Effect of oxide–semiconductor interface traps on low-temperature operation of MOSFETs

Lysenko, V. S.; Tyagulski, I.P.; Gomeniuk, Y. V.; Osiyuk, I. N.

doi:10.1016/s0026-2714(99)00295-4

Cited by 16 publications

(8 citation statements)

References 14 publications

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“…The current overshoot phenomenon occurred in Fig.4(e) at temperatures below 10K other than 15K [18] or 25K [19]. This phenomenon is related to the charge state of traps in the Si/SiO 2 interface.…”

Section: Current Overshoot and Discussionmentioning

confidence: 86%

Characterization and Modeling of 0.18μm Bulk CMOS Technology at Sub-Kelvin Temperature

Luo

et al. 2020

IEEE J. Electron Devices Soc.

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Previous cryogenic electronics studies are mostly at 77K and 4.2K. Cryogenic characterization of a 0.18µm standard bulk CMOS technology (operating voltages: 1.8V and 5V) is presented in this paper. Several NMOS and PMOS devices with different width to length ratios (W/L) were extensively tested and characterized under various bias conditions at sub-kelvin temperature. In addition to devices dc characteristics, the kink effect and current overshoot phenomenon are observed and discussed at sub-kelvin temperature. Especially, the current overshoot phenomenon in PMOS devices at sub-kelvin temperature is shown for the first time. The transfer characteristics of MOSFET devices (1.8V W/L = 10µm/10µm) at sub-kelvin temperature are modeled using the simplified EKV model. This work facilitates the CMOS circuits design and the integration of CMOS circuits with silicon-based quantum chips at extremely low temperatures.

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Section: Current Overshoot and Discussionmentioning

confidence: 86%

Characterization and Modeling of 0.18μm Bulk CMOS Technology at Sub-Kelvin Temperature

Luo

et al. 2020

IEEE J. Electron Devices Soc.

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“…In conventional bulk CMOS technology the major changes that need to adopt in analog circuit design are increased current factor (β) and threshold voltage (V th ) while the pronounced anomalies that have to overcome are 2 to 3 times increased mismatch compared to room temperature [9] and hysteresis and kink effect in the I-V characteristics curve of a MOS transistor. Kink occurs at the drain terminal due to the self-polarization of the bulk substrate nearly at the mid supply level [12] and on the other hand hysteresis takes place between the linear and saturation region due to the slow recharging rate of traps in the Si body and gate oxide interface [13]. Another CMOS technology -Silicon on Sapphire (SOS), specifically the fully depleted structure is reported to have superior response in room temperature and 4.2K due to the absence or less floating body effect [10], [14].…”

Section: Cryogenic Cmos Technologymentioning

confidence: 99%

A cryogenic DAC operating down to 4.2 K

Rahman

Lehmann

2016

Cryogenics

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This paper presents a 10 bit CMOS current steering digital to analog converter (DAC) that operates from room temperature to as low as 4.2K. It works as the core part of a cryogenic Silicon quantum computer controller circuit producing rapid control gate voltage pulses for quantum bits (qubits) initialization. An improved analog calibration method with a unique unit current cell design is included in the D/A converter structure to overcome the extended cryogenic nonlinear and mismatch effects. The DAC retains its 10 bit linear monotonic behavior over the wide temperature range and it drives a 50Ω load to 516mV with a full scale rise time of 10ns. The differential non-linearity (DNL) of the converter is 0.35LSB while its average power consumption is 32.18mW from a 3V power supply. The complete converter is fabricated using a commercial 0.5μm 1 poly 3 metal Silicon on Sapphire (SOS) CMOS process.

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“…Although it provides many advantages over room temperature like higher carrier mobility, faster switching speed, less parasitic capacit- ances and reduced interconnection delay [10,12], it also brings some drawbacks due to the dopants' inability of ionizing in low temperature. Fortunately this effect does not prevent the conduction process in a MOSFET but it gives rise to some profound nonlinearities like hysteresis [13] and kink effect [12]. Low temperature operation also gives unexpected threshold voltage variation as well as poor matching among similar devices and puts restriction on maximum power consumption.…”

Section: Cryogenic Cmos Technology Optionmentioning

confidence: 99%

Towards the implementation of a cryogenic D/A converter for silicon quantum computer controller

Rahman

Lehmann

2012

2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)

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A cryogenic CMOS D/A converter, core part of a Silicon quantum computer controller, produces voltage signals to generate electric fields for Silicon quantum bits initialization. In low temperature, the converter has to overcome several constraints before it is ready to work. These include CMOS operating region choice, anomalies of CMOS behavior, component mismatch degradation, technology choice and above all fulfilling the application requirements in cryogenic domain. In this paper, we explore these background requirements and critical issues that lead us to design a self calibrated ±1.5V 10 bit cryogenic D/A converter in 0.5µm CMOS Silicon-on-Sapphire process and briefly explain its architecture and design challenges. The differential nonlinearity (DNL) and integral nonlinearity (INL) of this converter are ±0.25 and ±0.4 least significant bit (LSB) respectively while its average power dissipation is 25mW and it occupies 1.2mm 2 die area.

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Effect of oxide–semiconductor interface traps on low-temperature operation of MOSFETs

Cited by 16 publications

References 14 publications

Characterization and Modeling of 0.18μm Bulk CMOS Technology at Sub-Kelvin Temperature

Characterization and Modeling of 0.18μm Bulk CMOS Technology at Sub-Kelvin Temperature

A cryogenic DAC operating down to 4.2 K

Towards the implementation of a cryogenic D/A converter for silicon quantum computer controller

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