Effect of Organic Additives on Ceria Slurry in Shallow Trench Isolation Chemical Mechanical Planarization

Abstract

An increase in the removal selectivity between silicon oxide and silicon nitride was attempted by adding organic additives to a ceria slurry for the application of shallow trench isolation (STI) chemical mechanical planarization (CMP). The protection behavior of poly(acrylic acid) (PAA) and the acceleration behavior of RE-610 in a ceria slurry were studied. PAA served as a protector of the silicon nitride due to the change in zeta potential. RE-610 worked as a hydration accelerator of the silicon oxide. When the two additives were added to the ceria slurry, the removal selectivity increased to 31:1. Moreover, PAA improved the stability of the ceria slurry.

Effect of Ceria Abrasives on Planarization Efficiency in STI CMP Process

“…The pad was conditioned by using an ex situ method, either prior to or after the wafers had been polished. The conditions were a pressure of 60 g/cm 2 and rotational velocity of 60 rpm, using a diamond segment type conditioner.…”

“…In order to analyze the planarization characteristics of ceria slurry, the first step of the STI CMP process was performed with the increase in polishing time at a pressure of 500 g/cm 2 and a rotational velocity of 60 rpm with carrier oscillation. An oxide patterned wafer of ~7000 Å thickness (SKW 3-2, SKW associates, Inc.) was used in this study, and the step height between the active oxide on Si 3 N 4 and the field oxide on Si in the STI pattern was about 6000 Å.…”

“…Table I describes the experimental conditions. The pressure ranged from 60-700 g/cm 2 . The Figure 2 shows planarization efficiency according to polishing time in the CMP using two slurries.…”

“…, respectively. Also, the units of RR , F , P , and V are Å/min, kg f , g/cm 2 , and m/min, respectively.…”

“…In particular, shallow trench isolation (STI) CMP has recently become a key technology for electrical isolation between transistors as the minimum feature size shrinks down to the sub-45nm level [2]. However, it is not easy to uniformly planarize the oxide feature on silicon wafer with nano-topography [3].…”