Effect of Doping Fluorine in Offset Region on Performance of Coplanar a-IGZO TFTs

Low‐Temperature Polysilicon Oxide Thin‐Film Transistors with Coplanar Structure Using Six Photomask Steps Demonstrating High Inverter Gain of 264 V V−1

“…Then, heavily doped n þ a-IGZO at the S/D contact regions were formed by exposing NF 3 plasma with the self-align process, as shown in Figure S1c,d, Supporting Information. [28,[39][40][41][42][43] The gate of LTPS TFT and LT-GI/HT-GI stack layer was patterned by wet and dry etching, respectively, with a PR covered on the n-type TFT region, as shown in Figure 1l and Figure S2a,b, Supporting Information. The p þ LTPS regions for S/D ohmic contact were B doped using an ion doping system using the self-align process, [44][45][46] as shown in Figure S2c,d, Supporting Information.…”

“…[12] The coplanar a-IGZO TFT needs an LT process for GI SiO 2 deposition to reduce the damage to the underlayer, oxide semiconductor. [25][26][27][28] LTPO TFTs with an etch stopper (ES) or back-channel etched (BCE) a-IGZO TFT with coplanar LTPS TFT are used for CMOS circuits. [13,14] Apple used coplanar a-IGZO TFT and coplanar LTPS TFT for LTPO array, but the a-IGZO TFT process starts after the whole process of LTPS TFT.…”

“…The Mo gate is wet etched, and LT-GI is dry etched using the self-align process, as shown in Figure S1a, Supporting Information. [28,[39][40][41][42] The design of n-gate with the remaining p-channel region is shown in Figure S1b, Supporting Information. F atoms are doped on the a-IGZO S/D region by NF 3 plasma treatment, [43] as shown in Figure S1c,d, Supporting Information.…”

“…The thermal activation by using rapid thermal annealing or furnace annealing could be used for dopant activation for the LTPS TFT process . The coplanar a‐IGZO TFT needs an LT process for GI SiO 2 deposition to reduce the damage to the underlayer, oxide semiconductor …”

25‐2: LTPO TFT Technology for Level Shifter Integrated Gate Driver in UHD 4K Displays

“…Finally, the devices are annealed at 250 ºC for 4h in a vacuum. Details of the coplanar single gate and dual gate TFT process are studied in our previous reports [8]- [9]. More details of the 6-mask LTPO fabrication process described in [2], [4]- [5].…”