Dynamic fault tolerance in FPGAs via partial reconfiguration

Emmert, John M.; Stroud, Charles E.; Skaggs, B.; Abramovici, M.

doi:10.1109/fpga.2000.903403

Cited by 80 publications

(43 citation statements)

References 14 publications

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“…Ambramovici et al [16]- [18] have demonstrated how self testing of small portions of a circuit can be carried out simultaneously with normal functioning of other parts. In [17], [18], a Self Testing Area, so called STAR, is first offloaded by reconfiguring its functionality on another area so that normal functioning is not affected at all, thus enabling online self testing using BIST (Built In Self Testing).…”

Section: Related Workmentioning

confidence: 99%

A Novel Approach for Providing Fault Tolerance to FPGA-Based Reconfigurable Systems

Sharma¹,

Chakraverty²

2012

IJET

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Abstract-Thedynamically reconfigurable Field Programmable Gate Arrays (FPGAs) are most frequently employed for developing adaptive embedded systems. They are also being increasingly used as co-processors in high performance computing applications. For these systems to be fielded in harsh environments such as those encountered in space, extra-terrestrial locations and regions of extreme conditions on the earth, one must adopt fault tolerant design techniques to ensure uninterrupted and reliable operation despite the occurrence of faults. Commercial Off-the-Shelf (COTS) FPGA components offer a cost effective design trajectory where the designer can choose among a rich variety of FT approaches and techniques. This paper compares the various FT techniques and proposes a novel method in which these techniques can work together to provide a synergetic approach for fault tolerant FPGA design.

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Section: Related Workmentioning

confidence: 99%

A Novel Approach for Providing Fault Tolerance to FPGA-Based Reconfigurable Systems

Sharma¹,

Chakraverty²

2012

IJET

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“…In [13][14][15], a method based on STARs (self-testing areas) is proposed to test specific offline actions of a device, and the STARs are moved across the FPGA to cover all the off-line sections [13][14][15]. Although STARs can mitigate permanent fault, they introduce a big time overhead and cannot correct permanent faults in module-based FPGAs.…”

Section: Introductionmentioning

confidence: 99%

Optimal Partial Reconfiguration for Permanent Fault Recovery on SRAM-Based FPGAs in Space Mission

Zhang

Guan

Mao

2013

Advances in Mechanical Engineering

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In this paper, we present a technique to maximize the lifetime of SRAM-based FPGAs in space mission. We focus on recovering permanent faults induced by SEE (single-events effect). In our technique, we use a fix-sized fault detection module to detect permanent faults and propose a permanent fault recovery mechanism for fault recovery. By using partial reconfiguration, we develop a system lifetime estimation model to find the optimal partition for designing the module-based fault recovering with the maximum system lifetime. We conduct experiments with a set of real applications including SpaceWire, Wavelet, AC97, MEPG-4, 8086, and Ethernet on Xilinx XUP platforms. The experimental results show our technique can effectively improve the lifetime compared with the previous work.

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“…By using DPR, the functionality of the system is reactively altered by replacing hardware modules according to, for example, user requests, performance requirements, or environmental changes. To date, various applications of DPR have been reported: content distribution security [1], low-power crypto-modules [2], video processing [3], automotive systems [4], faulttolerant systems [5] and software-defined radio [6] among others. It is expected that in the near future, it will be more popular for mobile terminals and consumer electronics to download hardware modules from the Internet in accordance with the intended use.…”

Section: Introductionmentioning

confidence: 99%

Bitstream Encryption and Authentication Using AES-GCM in Dynamically Reconfigurable Systems

Hori

Satoh

Sakane

et al. 2008

Advances in Information and Computer Security

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Abstract. A secure and dependable dynamic partial reconfiguration (DPR) system based on the AES-GCM cipher is developed, where the reconfigurable IP cores are protected by encrypting and authenticating their bitstreams with AES-GCM. In DPR systems, bitstream authentication is essential for avoiding fatal damage caused by inadvertent bitstreams. Although encryption-only systems can prevent bitstream cloning and reverse engineering, they cannot prevent erroneous or malicious bitstreams from being accepted as valid. If a bitstream error is detected after the system has already been partly configured, the system must be reconfigured with an errorless bitstream or at worst rebooted since the DPR changes the hardware architecture itself and the system cannot recover itself to the initial state by asserting a reset signal. In this regard, our system can recover from configuration errors without rebooting. To the authors' best knowledge, this is the first DPR system featuring both bitstream protection and error recovery mechanisms. Additionally, we clarify the relationship between the computation time and the bitstream block size, and derive the optimal internal memory size necessary to achieve the highest throughput. Furthermore, we implemented an AES-GCMbased DPR system targeting the Virtex-5 device on an off-the-shelf board, and demonstrated that all functions of bitstream decryption, verification, configuration, and error recovery work correctly. This paper clarifies the throughput, the hardware utilization, and the optimal memory configuration of said DPR system.

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Dynamic fault tolerance in FPGAs via partial reconfiguration

Cited by 80 publications

References 14 publications

A Novel Approach for Providing Fault Tolerance to FPGA-Based Reconfigurable Systems

A Novel Approach for Providing Fault Tolerance to FPGA-Based Reconfigurable Systems

Optimal Partial Reconfiguration for Permanent Fault Recovery on SRAM-Based FPGAs in Space Mission

Bitstream Encryption and Authentication Using AES-GCM in Dynamically Reconfigurable Systems

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