Bitstream Encryption and Authentication Using AES-GCM in Dynamically Reconfigurable Systems

Hori, Yohei; Satoh, Akashi; Sakane, Hitoshi; Toda, Kenji

doi:10.1007/978-3-540-89598-5_18

Cited by 32 publications

(15 citation statements)

References 17 publications

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“…Recently, this technology was applied to information and communication system security [14]. In computer security applications field, partial reconfiguration is applied in AES algorithm implementation [15]. It is also had been used to accelerate video processing in driver assistance system [16].…”

Section: Related Workmentioning

confidence: 99%

Partial Reconfiguration of Flux Limiter Functions in MUSCL Scheme Using FPGA

Talip

Akamine

Osana

et al. 2012

IEICE Trans. Inf. & Syst.

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SUMMARYComputational Fluid Dynamics (CFD) is used as a common design tool in the aerospace industry. UPACS, a package for CFD, is convenient for users, since a customized simulator can be built just by selecting desired functions. The problem is its computation speed, which is difficult to enhance by using the clusters due to its complex memory access patterns. As an economical solution, accelerators using FPGAs are hopeful candidate. However, the total scale of UPACS is too large to be implemented on small numbers of FPGAs. For cost efficient implementation, partial reconfiguration which dynamically loads only required functions is proposed in this paper. Here, the MUSCL scheme, which is used frequently in UPACS, is selected as a target. Partial reconfiguration is applied to the flux limiter functions (FLF) in MUSCL. Four FLFs are implemented for Turbulence MUSCL (TMUSCL) and eight FLFs are for Convection MUSCL (CMUSCL). All FLFs are developed independently and separated from the top MUSCL module. At start-up, only required FLFs are selected and deployed in the system without interfering the other modules. This implementation has successfully reduced the resource utilization by 44% to 63%. Total power consumption also reduced by 33%. Configuration speed is improved by 34-times faster as compared to full reconfiguration method. All implemented functions achieved at least 17 times speed-up performance compared with the software implementation. key words: computational fluid dynamics (CFD), field programmable gate array (FPGA), scientific computations, reconfigurable hardware, partial reconfiguration

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Section: Related Workmentioning

confidence: 99%

Partial Reconfiguration of Flux Limiter Functions in MUSCL Scheme Using FPGA

Talip

Akamine

Osana

et al. 2012

IEICE Trans. Inf. & Syst.

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“…For simplicity, we trust the management network and do not perform security checks on the incoming bitstreams. However, such functionality could be easily added [3].…”

Section: Implementation Detailsmentioning

confidence: 99%

NetStage/DPR: A Self-adaptable FPGA Platform for Application-Level Network Security

Mühlbach

Koch

2011

Lecture Notes in Computer Science

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Abstract. Increasing transmission speeds in high-performance networks pose significant challenges to protecting the systems and networking infrastructure. Reconfigurable devices have already been used with great success to implement lower-levels of appropriate security measures (e.g., deep-packet inspection). We present a reconfigurable processing architecture capable of handling even application-level tasks, and also able to autonomously adapt itself to varying traffic patterns using dynamic partial reconfiguration. As a first use-case, we examine the collection of Malware by emulating an entire honeynet of potentially hundreds of thousands of hosts using a single-chip implementation of the architecture.

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“…But such functionality could be easily added without affecting the base architecture (see, e.g., [6], [7]). …”

Section: A Partial Reconfiguration Processmentioning

confidence: 99%

A Dynamically Reconfigured Network Platform for High-Speed Malware Collection

Mühlbach

Koch

2010

2010 International Conference on Reconfigurable Computing and FPGAs

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Abstract-Malicious software has become a major threat to computer users on the Internet today. To combat it, security researchers need to gather and analyze many samples to develop proper defense mechanisms. The setting of honeypots, which emulate vulnerable applications, is one method of gathering attack code. In contrast to the conventional softwarebased honeypots, we have proposed a dedicated hardware architecture for honeypots to both allow high-speed operation at rates of 10+ Gb/s as well as a higher resilience against attacks on the honeypot infrastructure itself. We now improve the flexibility of our prior solution by using partial dynamic reconfiguration to update the functionality of the honeypot during operation.

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Bitstream Encryption and Authentication Using AES-GCM in Dynamically Reconfigurable Systems

Cited by 32 publications

References 17 publications

Partial Reconfiguration of Flux Limiter Functions in MUSCL Scheme Using FPGA

Partial Reconfiguration of Flux Limiter Functions in MUSCL Scheme Using FPGA

NetStage/DPR: A Self-adaptable FPGA Platform for Application-Level Network Security

A Dynamically Reconfigured Network Platform for High-Speed Malware Collection

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