Optimal Partial Reconfiguration for Permanent Fault Recovery on SRAM-Based FPGAs in Space Mission

Abstract

In this paper, we present a technique to maximize the lifetime of SRAM-based FPGAs in space mission. We focus on recovering permanent faults induced by SEE (single-events effect). In our technique, we use a fix-sized fault detection module to detect permanent faults and propose a permanent fault recovery mechanism for fault recovery. By using partial reconfiguration, we develop a system lifetime estimation model to find the optimal partition for designing the module-based fault recovering with the maximum system lifetime. We conduct experiments with a set of real applications including SpaceWire, Wavelet, AC97, MEPG-4, 8086, and Ethernet on Xilinx XUP platforms. The experimental results show our technique can effectively improve the lifetime compared with the previous work.

Reliability and Makespan Optimization of Hardware Task Graphs in Partially Reconfigurable Platforms

“…As indicated by [26], different altitudes above the Earth surface have different soft error rates (SERs) that can be measured per bit per time unit. In this work, the reliability model presented in [27] has been used.…”

“…, in which µ is the SER expressed in bit per time unit [26], CT i is task computation time, and RT i is residency time of Task τ i indicating the time elapsed from when it is configured until it starts its execution. The SER can be estimated by some modeling tools such as CREME96 [28].…”

“…Based on the values of soft errors reported in [26], for difference altitudes of harsh environments, SERs take values ranging between 1.0 × 10 −7 to 5.0 × 10 −3 upsets per bit per day. By having a task graph and the SER, MTTF of tasks and task graphs before and after applying FT techniques can be easily obtained from Eqs.…”

Reliability Improvement of Hardware Task Graphs via Configuration Early Fetch

“…As indicated by [41], different altitudes above the Earth surface have different Soft Error Rates (SERs). In this paper, the reliability model presented in our previous work [42] has been used to estimate the reliability of a hardware task τ (denoted as R τ ).…”

“…in which ρ is the SER expressed in #SEUs per bit per time unit [41], T S τ is task size in configuration memory, SB τ indicates the percent of sensitive bits of Task τ [43], CT τ is task computation time, and RT τ is residency time of Task τ , indicating the time elapsed from when it is configured until it starts its execution. As this shows, despite the prefetch techniques increase the system performance, they also increase the probability of upsets in the task, which leads to the reliability degradation.…”