Dynamic Context Compression for Low-Power Coarse-Grained Reconfigurable Architecture

Kim, Yoonjin; Mahapatra, Rabi

doi:10.1109/tvlsi.2008.2006846

Cited by 41 publications

(26 citation statements)

References 14 publications

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“…Table 7 shows the compression ratio comparison with both post-context-generation methods. As can be seen, the proposed method outperforms both dictionary-based compression [8] and dynamic compression [7]. Considering both of them need extra hardware support, the proposed method has more obvious advantages.…”

Section: Comparison With Post-context-generation Methodsmentioning

confidence: 89%

“…We also compare our proposed method with two postcontext-generation methods, DCC [7] and CS3 [8], in terms of the context compression ratio and execution performance. Table 6 shows the comparison results for context size and compression ratio.…”

Section: Comparison With Post-context-generation Methodsmentioning

confidence: 99%

“…They designed a two-step coder: the configuration bitstream is adaptively filtered to remove data redundancy in the first step, while in the second step an arithmetic coder is used to actually compress the bitstream. Dynamically compressible context architecture for power saving in configuration cache can be found in [7]. This power-efficient design of context architecture works without degrading the performance and flexibility of coarse-grained reconfigurable architecture.…”

Section: Introductionmentioning

confidence: 99%

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Configuration Context Reduction for Coarse-Grained Reconfigurable Architecture

Yin

Liu

et al. 2012

IEICE Trans. Inf. & Syst.

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SUMMARYCoarse-grained reconfigurable architecture (CGRA) combines the performance of application-specific integrated circuits (ASICs) and the flexibility of general-purpose processors (GPPs), which is a promising solution for embedded systems. With the increasing complexity of reconfigurable resources (processing elements, routing cells, I/O blocks, etc.), the reconfiguration cost is becoming the performance bottleneck. The major reconfiguration cost comes from the frequent memory-read/write operations for transferring the configuration context from main memory to context buffer. To improve the overall performance, it is critical to reduce the amount of configuration context. In this paper, we propose a configuration context reduction method for CGRA. The proposed method exploits the structure correlation of computation tasks that are mapped onto CGRA and reduce the redundancies in configuration context. Experimental results show that the proposed method can averagely reduce the configuration context size up to 71% and speed up the execution up to 68%. The proposed method does not depend on any architectural feature and can be applied to CGRA with an arbitrary architecture.

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Section: Comparison With Post-context-generation Methodsmentioning

confidence: 89%

Section: Comparison With Post-context-generation Methodsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Configuration Context Reduction for Coarse-Grained Reconfigurable Architecture

Yin

Liu

et al. 2012

IEICE Trans. Inf. & Syst.

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“…Kim et al provide yet another solution in which the configuration bits of one column in one cycle are reused for the next column in the next cycle [30]. Furthermore, they also propose to reduce the power consumption in the configuration memories by compressing the configurations [29].…”

Section: Reconfigurabilitymentioning

confidence: 99%

Coarse-Grained Reconfigurable Array Architectures

Sutter

Raghavan

Lambrechts

2010

Handbook of Signal Processing Systems

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Coarse-Grained Reconfigurable Array (CGRA) architectures accelerate the same inner loops that benefit from the high ILP support in VLIW architectures. By executing non-loop code on other cores, however, CGRAs can focus on such loops to execute them more efficiently. This chapter discusses the basic principles of CGRAs, and the wide range of design options available to a CGRA designer, covering a large number of existing CGRA designs. The impact of different options on flexibility, performance, and power-efficiency is discussed, as well as the need for compiler support. The ADRES CGRA design template is studied in more detail as a use case to illustrate the need for design space exploration, for compiler support and for the manual fine-tuning of source code.

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“…With the requirements for higher performance and flexibility in embedded design, reconfigurable computing [1,2,3] is becoming more promising than application specific integrated circuit (ASIC) and digital signal processor (DSP). Reconfigurable architectures have been proposed as a compromise approach as they are flexible, scalable and can provide reasonable computing capability.…”

Section: Introductionmentioning

confidence: 99%

Design and implementation of high performance matrix inversion based on reconfigurable processor

Wang

Feng

et al. 2016

IEICE Electron. Express

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In this paper, we propose a high performance matrix inversion implementation on a reconfigurable application specific processor. Our implementation can accelerate variable order matrix inversion ranging from 4 to 144. We adopt LU decomposition to reduce the computation complexity and a pivoting operation to ensure the stability. In order to get higher performance within the limited resources, parallel computing and timesharing multiplexing are employed. The chip testing results show that our implementation improve the performance of inversion efficiently. The highest parallel speed-up ratio can achieve 3 times, and the execution time of a 144 × 144 matrix inversion is 4.07 ms.

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Dynamic Context Compression for Low-Power Coarse-Grained Reconfigurable Architecture

Cited by 41 publications

References 14 publications

Configuration Context Reduction for Coarse-Grained Reconfigurable Architecture

Configuration Context Reduction for Coarse-Grained Reconfigurable Architecture

Coarse-Grained Reconfigurable Array Architectures

Design and implementation of high performance matrix inversion based on reconfigurable processor

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