Dual Active-Feedback Frequency Compensation for Output-Capacitorless LDO With Transient and Stability Enhancement in 65-nm CMOS

Li, Guangxiang; Huimin, Qian; Guo, Jianping; Mo, Bing; Lü, Yan; Chen, Dihu

doi:10.1109/tpel.2019.2910557

Cited by 70 publications

(34 citation statements)

References 21 publications

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“…First, let us analyse the test setup described in [14] for measuring the load transient response of an LDO, depicted in Fig. 22.a).…”

Section: B Silicon Implementation and Measurement Resultsmentioning

confidence: 99%

“…22.a), creates a charge-injection path between the large control signal applied to the NMOS gate and CL. Therefore, the output voltage undershoot/overshoot cannot be accurately measured with this setup [14]. The new test setup proposed in Fig.…”

Section: B Silicon Implementation and Measurement Resultsmentioning

confidence: 99%

“…But this is only true if V1&V2 exhibit relatively small variations during LDO output voltage transients. This is not the case here -in fact, neither is in [13] or [14]. Transistors M4B/M9 (M7/M4 in [13], M20/M23 in [14]) will pull V1&V2 to GND/VIN during large output voltage undershoots/overshoots, significantly reducing the voltage variation dV /dt across C 1 and C 2 .…”

Section: A Schematic and Principle Of Operationmentioning

confidence: 86%

“…It can be argued that the same effect can be achieved with fewer components by connecting capacitors C 1 and C 2 to nodes 1 & 2 (the sources of M5 and M7, respectively), as proposed in [13] and [14]. But this is only true if V1&V2 exhibit relatively small variations during LDO output voltage transients.…”

Section: A Schematic and Principle Of Operationmentioning

confidence: 98%

“…2 capacitors C 1 , C 2 and resistors R connected to the sources of transistors M4B and M9 -implements a capacitance multiplier with the gain approximately 2G m F Z G , largely independent on the load current and capacitance. As explained in Section II.A, [13], [14] proposed a fairly similar, but less effective, topology.…”

Section: Analysis Of T I N N E R For a P M T I N N E R ≥ 45mentioning

confidence: 99%

See 4 more Smart Citations

LDO With Improved Common Gate Class-AB OTA Handles any Load Capacitors and Provides Fast Response to Load Transients

Răducan

Grajdeanu

Plesa

et al. 2020

IEEE Trans. Circuits Syst. I

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This article proposes an LDO with fast response to load transients that can handle any practical capacitive loads. These features are mainly due to a novel frequency compensation circuit tailored for its error amplifier, which is based on an improved version of the popular common gate amplifier. A simple yet effective approach to the small-signal analysis of LDO with multiple feedback loops is employed to analyse intuitively the LDO and derive key design constraints. Simulation and measurement results performed on a test chip implemented in standard 130nm CMOS process validated the proposed LDO. It requires only 0.7µA quiescent current but exhibits an excellent response to load transients: when the load current jumps from 0A to 100mA in 1µs the output voltage presents an undershoot of 76mV and an overshoot of 198mV, without decoupling capacitors. It compares well against seven LDOs designed with common gate error amplifiers for similar levels of supply voltage, output voltage and current and against seven fast LDOs employing different error amplifiers. A figureof-merit that considers the quiescent current, the maximum load current and capacitance, as well as the output voltage deviation, yielded a value for our LDO 39.8 times better than for the nearer competitor that employs common gate amplifier and 6 times better than the one employing a different error amplifier. When considering edge time and process scaling the performance of the proposed LDO is 4.8, respectively 4.5, times better than the second best in both comparisons.

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“…First, let us analyse the test setup described in [14] for measuring the load transient response of an LDO, depicted in Fig. 22.a).…”

Section: B Silicon Implementation and Measurement Resultsmentioning

confidence: 99%

Section: B Silicon Implementation and Measurement Resultsmentioning

confidence: 99%

Section: A Schematic and Principle Of Operationmentioning

confidence: 86%

Section: A Schematic and Principle Of Operationmentioning

confidence: 98%

Section: Analysis Of T I N N E R For a P M T I N N E R ≥ 45mentioning

confidence: 99%

See 3 more Smart Citations

LDO With Improved Common Gate Class-AB OTA Handles any Load Capacitors and Provides Fast Response to Load Transients

Răducan

Grajdeanu

Plesa

et al. 2020

IEEE Trans. Circuits Syst. I

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Bird's‐eye view of analog and mixed‐signal chips for the 21st century

Martins

Mak

Chan

et al. 2021

Circuit Theory & Apps

Self Cite

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SUMMARY The Internet of Everything (IoE), clearly a 21st century's technology, brilliantly plays with digital data obtained from analog sources, bringing together two different realities, the analog (physical/real), and the digital (cyber/virtual) worlds. Then, with the boundaries of IoE still analog in nature, the required functions at the interface involve sensing, measuring, filtering, converting, processing, and connecting, which imply that the analog layer governs the entire system in terms of accuracy and precision. Furthermore, such interface integrates several analog and mixed‐signal subsystems that comprise mainly signal transmission and reception, frequency generation, energy harvesting, data, and power conversion. This paper sets forth a state‐of‐the‐art design perspective of some of the most critical building blocks used in the analog/digital interface, covering wireless cellular transceivers, millimeter‐wave frequency generators, energy harvesting interfaces, plus, data and power converters, that exhibit high quality performance achieved through low‐power consumption, high energy‐efficiency, and high speed.

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A Novel Frequency Compensation Scheme for Heavy Load LDO with Improved Load Regulation and High Open Loop Gain

Wang

Zhao

et al. 2023

IEEJ Transactions Elec Engng

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This paper presents a novel frequency compensation scheme for the stability of low dropout regulator (LDO). The proposed compensation scheme introduces a zero in the voltage regulation loop to enlarge gain and phase margin at high‐frequencies. As a result, high open‐loop‐gain and improved load regulation performances are achieved, and a particular resistor is introduced in the compensation structure to cancel the voltage drop originating from cable resistances at the output to further improve the load regulation performance. The proposed LDO with wide input/output range and high‐power supply rejection is designed and implemented in a 180 nm CMOS process. The LDO operates with an input voltage range of 4–16 V, an output voltage range of 1.5–5 V and an output current range of 0–1000 mA. High open loop gain and high bandwidth are achieved, and the simulated performances of load regulation and line regulation are less than 32 μV/mA and less than 3 mV/V over the whole operation range, respectively. The on‐chip compensation capacitor required by the compensation module is only 1.8 pF. © 2023 Institute of Electrical Engineers of Japan. Published by Wiley Periodicals LLC.

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Dual Active-Feedback Frequency Compensation for Output-Capacitorless LDO With Transient and Stability Enhancement in 65-nm CMOS

Cited by 70 publications

References 21 publications

LDO With Improved Common Gate Class-AB OTA Handles any Load Capacitors and Provides Fast Response to Load Transients

LDO With Improved Common Gate Class-AB OTA Handles any Load Capacitors and Provides Fast Response to Load Transients

Bird's‐eye view of analog and mixed‐signal chips for the 21st century

A Novel Frequency Compensation Scheme for Heavy Load LDO with Improved Load Regulation and High Open Loop Gain

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