2004
DOI: 10.1109/ted.2004.825821
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Drain disturb during CHISEL programming of NOR flash EEPROMs-physical mechanisms and impact of technological parameters

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Cited by 26 publications
(20 citation statements)
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“…11 shows the impact of technology parameters on charge gain drain disturb and P/D margin before and after 100 K P/E cycles under CHE operation. Note that CHE shows charge loss disturb at much higher values than used in this work [19]. Contrary to CHISEL operation, cells with lower junction depth show lower initial and degraded and correspondingly higher P/D margin.…”
Section: B Optimization Of Nonhalo Cellsmentioning
confidence: 73%
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“…11 shows the impact of technology parameters on charge gain drain disturb and P/D margin before and after 100 K P/E cycles under CHE operation. Note that CHE shows charge loss disturb at much higher values than used in this work [19]. Contrary to CHISEL operation, cells with lower junction depth show lower initial and degraded and correspondingly higher P/D margin.…”
Section: B Optimization Of Nonhalo Cellsmentioning
confidence: 73%
“…7 shows the drain disturb time before and after 100 K P/E cycles as a function of FG length for halo and nonhalo (LL) cells, under both charge gain and loss disturb modes. It has been previously identified that unlike CHE operation, CHISEL operation shows both charge gain and loss disturb that originates from band-to-band tunneling (BTBT) [19]. BTBT generated electrons (holes) get heated by the junction field and get attracted toward the FG by positive FG charge in erased state (by negative FG charge during erase state) and cause charge gain (charge loss) disturb.…”
Section: A Comparison Between Halo and Nonhalo Cellsmentioning
confidence: 99%
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“…CGD is shown to be due to hot-electron injection into the FG, with the source of hot electrons being different for CHE and CHISEL operations [20]. The sources behind CGD are shown to be channel leakage (drain-induced turn-on) and BTBT under CHE and CHISEL operations, respectively.…”
Section: A Effect Of Substrate Bias On Program and Drain Disturbmentioning
confidence: 95%
“…Program drain disturb is one of the serious reliability concerns of NOR flash EEPROMs that causes V TH shift in drain stressed cells (cells sharing the same bit line as the cell being programmed but having an unselected word line) [1], [19]. CHE drain disturb originates from subthreshold channel leakage [2] and worsens when L FG is scaled, whereas CHISEL drain disturb originates from band-to-band-tunneling (BTBT) at drain junction [10], [20] and worsens when source-drain (S/D) junction depth (X J ) is scaled. Hence, drain disturb can be a serious concern with cell scaling.…”
mentioning
confidence: 99%