Cycling Endurance of NOR Flash EEPROM Cells Under CHISEL Programming Operation—Impact of Technological Parameters and Scaling

Abstract

Abstract-The impact of technological parameter (channel doping, source/drain junction depth) variation and channel length scaling on the reliability of NOR Flash EEPROM cells under channel initiated secondary electron (CHISEL) programming is studied. The best technology for CHISEL operation has been identified by using a number of performance metrics (cycling endurance of program/erase time, program/disturb margin) and scaling studies were done on this technology. It is explicitly shown that from a reliability perspective, bitcell optimization for CHISEL operation is quite different from that for channel hot electron (CHE) operation. Properly optimized bitcells show reliable CHISEL programming for floating gate length down to 0.2 m.Index Terms-Band-to-band tunneling, channel hot electron (CHE), channel initiated secondary electron (CHISEL), device scaling, drain disturb, Flash EEPROMs, hot carriers.

Explanation of P/E Cycling Impact on Drain Disturb in Flash EEPROMs Under CHE and CHISEL Programming Operation

“…Measurements were performed on isolated, fully scaled bitcells having finished of 0.3 through 0.2 m, width (W) of 0.3 m, tunnel oxide and ONO interpoly dielectric (IPD) thickness of 12 and 20 nm, respectively and gate coupling of about 0.55. The devices used in this paper are of HL type [17].…”

“…It has also been shown that drain disturb after P/E cycling increases for the charge gain mode (from erased cells) and decreases for the charge loss mode (from programmed cells), for cycling under a wide range of drain and control-gate biases [15], [16]. Furthermore, the impact of technological parameters on drain disturb (both before and after cycling) has also been extensively studied [17]. However, to the best of our knowledge, the mechanism behind the impact of P/E cycling on drain disturb has not been convincingly explained so far [16].…”

“…Built on our previous work [14]- [17], this paper uses carefully designed experiments and fullband Monte Carlo simulations to explain the post-cycling behavior of drain disturb under CHE and CHISEL operation. Device and experimental details are listed in Section II, results are presented and discussed in Section III and concluded in Section IV.…”

Yet Another Hydrodynamic Model with Correlated Parameters for Silicon Devices

“…Some recent studies demonstrated the important role of lattice heat and thermal activation of the lo w voltage impact ionization in deep-submicro meter M OSFETs [132]. In addition, the recent studies of silicon on insulator (SOI) devices by the classical HDM , showed certain anomalies due to lack of a heat evacuation mechanism at the insulator interface [133].…”

Using Soft Secondary Electron Programming to Reduce Drain Disturb in Floating-Gate NOR Flash EEPROMs

“…Compared with CHE, CHISEL offers faster program speed under equivalent power, lower power consumption under similar speed, better cycling endurance of V TH window, and lower degradation of program time T P [6], [9], [10], [16], [17]. CHISEL also leads to a selfconvergent programming, giving a better control over program V TH [4], [6], [11].…”