Disturbless flash memory due to high boost efficiency on BiCS structure and optimal memory film stack for ultra high density storage device

Abstract

Program and erase operation on NAND-string of Bit-Cost Scalable (BiCS) flash memory has been successfully achieved. High boost efficiency of floating pillars and ONON (block oxide/charge SiN/tunnel oxide/tunnel SiN) structure as a memory film stack improve disturbance characteristics enough to realize tera-bit density of three dimensional flash memory. BiCS flash memory has become a more promising candidate for ultra high density memory.

Review of Emerging New Solid-State Non-Volatile Memories

“…To extend bit-cost scaling while avoiding the parasitic effect, a flash memory that has a vertical NAND string was first proposed by Endoh et al 3) After that, a lot of flash memories with similar three-dimensional (3D) structures were proposed. [4][5][6][7][8][9][10][11][12] An example of a 3D flash is shown in Fig. 1.…”

“…4) This structure is called ''BiCS'', which is taken from the expression ''bit cost scalable''. [4][5][6] The concept on which this structure is based is to make a footprint of one cell smaller by stacking multiple cells in one area. In the case that 16 cells are stacked in one area, the area per cell becomes 16 times smaller than that of a non-stacked structure, if the area penalty of the stacked structure is ignored (Regarding the area penalty, refer to Refs.…”

“…In the case that 16 cells are stacked in one area, the area per cell becomes 16 times smaller than that of a non-stacked structure, if the area penalty of the stacked structure is ignored (Regarding the area penalty, refer to Refs. [4][5][6][7][8][9][10][11][12]. Although the 3D structure has been the long-term dream of ''ultimate integration'' since LSIs began to be fabricated, no product with a 3D structure has ever been realized, because of the high fabrication cost and low yield involved.…”

“…In the case of BiCS, the lower limit of the hole is expected to be approximately 32 nm. [4][5][6] Therefore, unlike in the case of two-dimensional (2D) flash memories, further advances in lithography technology will not have much effect in terms of increasing the memory capacity of BiCS flash. Other 3D NAND flash memories, such as the stacked-surrounding gate transistor (S-SGT 3) ) structured cell, the extended sidewall control gate (ESCG 11) ), the separated-sidewall control gate (S-SCG 12) ), the terabit-cellarray transistors (TCATs 8) ), the vertical-gate (VG) NAND, 9) and the dual-control-gate and surrounding-floating-gate (DCSF) NAND, 10) also have similar limitations for 2D miniaturization.…”

Body Doping Profile of Select Device to Minimize Program Disturbance in Three-Dimensional Stack NAND Flash Memory

“…[1][2][3][4][5][6][7][8][9][10] The conventional planar 2D NAND flash memory is likely to face fundamental scaling limitations mainly coming from lithography and electrical coupling. Such fundamental barriers can be overcome with the scaling-up of physical dimension (larger than planar design rule) by introducing 3D cell structures.…”