Dislocations in Relaxed SiGe/Si Heterostructures

Fitzgerald, Eugene A.; Currie, M. T.; Samavedam, Srikanth; Langdo, T. A.; Taraschi, Gianni; Yang, V. K.; Leitz, Christopher; Bulsara, Mayank T.

doi:10.1002/(sici)1521-396x(199901)171:1<227::aid-pssa227>3.0.co;2-y

Cited by 75 publications

(25 citation statements)

References 16 publications

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“…As long as these threading dislocation arms do not annihilate or get trapped at boundaries, they extend through the entire layer along the (111) planes until they terminate at the layer surface. 35 The stress fields associated with these threading dislocations cause a local deformation of the crystal lattice planes, which can be imaged using ECCI, as described in the Experimental section. As a consequence, each of the dot-like features visible in the ECCI micrograph shown in Fig.…”

Section: Resultsmentioning

confidence: 99%

Non-destructive characterization of extended crystalline defects in confined semiconductor device structures

et al. 2018

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Semiconductor heterostructures are at the heart of most nanoelectronic and photonic devices such as advanced transistors, lasers, light emitting diodes, optical modulators and photo-detectors. However, the performance and reliability of the respective devices are often limited by the presence of crystalline defects which arise from plastic relaxation of misfit strain present in these heterogeneous systems. To date, characterizing the nature and distribution of such defects in 3D nanoscale devices precisely and non-destructively remains a critical metrology challenge. In this paper we demonstrate that electron channeling contrast imaging (ECCI) is capable of analyzing individual dislocations and stacking faults in confined 3D nanostructures, thereby fulfilling the aforementioned requirements. For this purpose we imaged the intensity of electrons backscattered from the sample under test under controlled diffraction conditions using a scanning electron microscope (SEM). In contrast to transmission electron microscopy (TEM) analysis, no electron transparent specimens need to be prepared. This enables a significant reduction of the detection limit (i.e. lowest defect density that can be assessed) as our approach facilitates the analysis of large sampling volumes, thereby providing excellent statistics. We applied the methodology to SiGe nanostructures grown by selective area epitaxy to study in detail how the nature and distribution of crystalline defects are affected by the dimensions of the structure. By comparing our observations with the results obtained using X-ray diffraction, TEM and chemical defect etching, we could verify the validity of the method. Our findings firmly establish that ECCI must be considered the method of choice for analyzing the crystalline quality of 3D semiconductor heterostructures with excellent precision even at low defect densities. As such, the technique aids in better understanding of strain relaxation and defect formation mechanisms at the nanoscale and, moreover, facilitates the development and fabrication of next generation nanoelectronic and photonic devices.

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Section: Resultsmentioning

confidence: 99%

Non-destructive characterization of extended crystalline defects in confined semiconductor device structures

et al. 2018

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“…The latter can be reduced by special additional measures connected mostly with the growth of much thicker graded or constant composition layers, or with additional ex situ treatment. [1][2][3][4] Thus, SRB with small thickness, high Ge content, and high degree of relaxation is a rather ambitious aim. In order to lattice match SiGe buffer layers with the Si substrate, a controlled introduction of point defects at the beginning of SiGe buffer epitaxial growth, below the critical thickness, was proposed in Refs.…”

Section: Introductionmentioning

confidence: 99%

Composition and strain in thin Si1−xGex virtual substrates measured by micro-Raman spectroscopy and x-ray diffraction

Perova¹,

Wasyluk²,

Lyutovich³

et al. 2011

Journal of Applied Physics

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Micro-Raman spectroscopy was employed for the determination of the germanium content, x and strain, , in ultrathin SiGe virtual substrates grown directly on Si by molecular beam epitaxy. The growth of highly relaxed SiGe layers was achieved by the introduction of point defects at a very low temperature during the initial stage of growth. SiGe virtual substrates with thicknesses in the range 40-200 nm with a high Ge content ͑up to 50%͒ and degree of relaxation, r, in the range 20%-100% were investigated using micro-Raman spectroscopy and x-ray diffraction ͑XRD͒ techniques. The Ge content, x, and strain, , were estimated from equations describing Si-Si, Si-Ge, and Ge-Ge Raman vibrational modes, modified in this study for application to thin SiGe layers. The alteration of the experimentally derived equations from previous studies was performed using independent data for x and r obtained from XRD reciprocal space maps. A number of samples consisting of a strained-silicon ͑s-Si͒ layer deposited on a SiGe virtual substrate were also analyzed. The stress value for the s-Si varied from 0.54 to 2.75 GPa, depending on the Ge-content in the virtual substrates. These results are in good agreement with theoretically predicted values.

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“…Strained SiGe [19], SiGe x C y based alloys or strained Si epitaxy have been studied to increase the channel mobility [17] [20] by introducing compressive or tensile strain to enhance hole or electron effective mass respectively. In order to achieve such channel architectures, bulk relaxed SiGe pseudo substrates obtained by graded SiGe buffer were intensively developed during the last decades [ [21], [22]]. High-quality pseudomorphic silicon layer with very high biaxial-strain values (typically 1.2-1.5 MPa or more) can be grown on those substrates.…”

Section: Gate Stack and Channel/substrate Engineeringmentioning

confidence: 99%

Cmos Devices Architectures and Technology Innovations for the Nanoelectronics Era

Deleonibus¹,

Salvo²,

Ernst³

et al. 2006

Int. J. Hi. Spe. Ele. Syst.

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Innovations in electronics history have been possible because of the strong association of devices and materials research. The demand for low voltage, low power and high performance are the great challenges for engineering of sub 50nm gate length CMOS devices. Functional CMOS devices in the range of 5 nm channel length have been demonstrated. The alternative architectures allowing to increase devices drivability and reduce power are reviewed through the issues to address in gate/channel and substrate, gate dielectric as well as source and drain engineering. HiK gate dielectric and metal gate are among the most strategic options to consider for power consumption and low supply voltage management. It will be very difficult to compete with CMOS logic because of the low series resistance required to obtain high performance. By introducing new materials(Ge, diamond/graphite Carbon, HiK,...), Si based CMOS will be scaled beyond the ITRS as the future System-on-Chip Platform integrating new disruptive devices. The association of C-diamond with HiK as a combination for new functionalized Buried Insulators, for example, will bring new ways of improving short channel effects and suppress self-heating. That will allow new optimization of Ion-Ioff trade offs. The control of low power dissipation and short channel effects together with high performance will be the major challenges in the future. Int. J. Hi. Spe. Ele. Syst. 2006.16:193-219. Downloaded from www.worldscientific.com by UNIVERSITY OF AUCKLAND LIBRARY -SERIALS UNIT on 03/24/15. For personal use only. Limitations and showstoppers coming from classical bulk CMOS scaling.CMOS device engineering consists in minimizing leakage current together with the maximization of output current. In sub lOOnm CMOS devices, non stationary transport gains more importance as compared to diffusive transport. Int. J. Hi. Spe. Ele. Syst. 2006.16:193-219. Downloaded from www.worldscientific.com by UNIVERSITY OF AUCKLAND LIBRARY -SERIALS UNIT on 03/24/15. For personal use only.

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Dislocations in Relaxed SiGe/Si Heterostructures

Cited by 75 publications

References 16 publications

Non-destructive characterization of extended crystalline defects in confined semiconductor device structures

Non-destructive characterization of extended crystalline defects in confined semiconductor device structures

Composition and strain in thin Si1−xGex virtual substrates measured by micro-Raman spectroscopy and x-ray diffraction

Cmos Devices Architectures and Technology Innovations for the Nanoelectronics Era

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