Discrete-Time, Linear Periodically Time-Variant Phase-Locked Loop Model for Jitter Analysis

Abstract

Abstract-Timing jitter is one of the most significant phase-locked loop (PLL) characteristics, which directly affects the performance of the system in which the PLL is used. It is, therefore, important to develop the tools necessary to study and predict PLL jitter performance at design time. In this paper a discrete-time, linear, periodically time-variant integer-PLL model for jitter analysis is proposed, which accounts for the periodically time-varying effect of noise injected into the loop at various PLL components, such as VCO, charge pump, VCO buffer, VCO control node, and divider. The model also predicts the aliasing of jitter due to the downsampling and upsampling of the jitter signal around the PLL loop. Closed-form expressions are derived for the output jitter spectrum and match well with results of event-driven simulations of a third-order PLL.

Analysis of VCO Phase Noise in Charge-Pump Phase-Locked Loops

“…Then, by applying the aforementioned Theorem to the first term in (11), we find (12) Hence, Fourier transforming both sides of (12), we derive the following spectrum of the CP current: (13) where and . The PLL output is related to the CP current via the following time-domain relationship: (14) that in the frequency domain transforms to (15) Thus, by plugging (13) into (15), we finally obtain (16) where (17) In the remainder of this section, we focus on the noise contribution given by the VCO that we rewrite as (18) In the case of a purely random noise , the noise transfer function (18) is better formulated in terms of the power spectral densities (PSDs) [24] of the VCO and PLL output phase-noise, respectively, as follows: (19) Equations (18) and (19) show that the VCO phase-noise is transferred to the PLL output through two different paths: the first one that directly involves the VCO noise spectrum (or related power spectrum ); the second one that operates on its folded version (or related folded power spectrum ) and that results from the subsampling operated by the PFD.…”

“…However, its extension to determine the noise transfer functions is not straightforward when the PLL contains a frequency divider. In this case, two frequency domains coexist in the loop (one operating at the low reference frequency and the other one working at the high output frequency) and the subsampling operated by the PFD on phase noise and periodic disturbances can result in relevant extra in-band noise contributions and unexpected spurs [13].…”

Derivation of a Small-Signal Harmonic Model for Closed-Loop Power Converters Based on the State-Variable Sensitivity Method

“…LTI transfer functions have no coupling between different orders of harmonics and consequently only diagonal terms exist in the harmonic matrices. More elaborate explanations on the difference between LTV and LTI systems can be found in [42], [54], [63] and [64].…”

Design and implementation of a compact frequency synchronisation control circuit using enable input for DC–DC converter

“…The internal oscillator frequency is locked by an external clock signal to synchronise the switching frequency. However, the PLL and DLL approaches increase the chip area and the cost because of the drawbacks of complex loop design and the phase noise and jitter issue [12][13][14]. This paper presents a frequency synchronisation control circuit which uses an external clock signal to control the switching frequency directly instead of the internal oscillator frequency.…”