Design and implementation of a compact frequency synchronisation control circuit using enable input for DC–DC converter

Abstract

This study presents a compact frequency synchronisation control circuit using enable input for a DC -DC converter. The circuit extracts both enable signal and external synchronous clock from EN pin, which eases the system design and reduces the cost. The external clock can be recognised by setting a synchronous frequency range and replace the internal oscillator clock to synchronise the switching frequency directly without using a phase-locked loop. The proposed circuit has been implemented in a 0.6 mm complementary metal oxide semiconductor (CDMOS) process high-voltage buck DC -DC converter. The test results indicate that both enable and external synchronisation function can be realised by control of EN pin. Better performance has been achieved.

Low‐quiescent‐current flexible mode buck–boost converter

“…We can conclude from Fig. 2 that DRVA, DRVB and PWM_AB are always in the same phase [12, 14–16], so are the signals DRVC, DRVD and CD.…”

Reliability evaluation of a fault-tolerant three-phase interleaved DC-DC boost converter

“…DC–DC power converters have been extensively used in many industrial applications such as portable electronic devices, satellite and renewable energy applications owing to their suitable characteristics, such as high efficiency, small size, wide range of output voltage and simple design of controller (Benzaouia et al, 2016; Fesharaki et al, 2017; Lui et al, 2012; Moreno-Valenzuela et al, 2016; Rahimi et al, 2016). As reported in Walker and Sernia (2004), Alam and Khan (2014) and Hwang and Park (2012), conventional boost converters have suitable characteristics such as simple structure and easy control.…”

Zero‐steady‐state‐error compensation method in application of peak current mode buck converter with fast transient response

“…The analysis in Sections 3 and 4 proves that small signal transfer function from the output of EA to inductor current can be treated as a constant value. In Section 5, the small signal model of the ZSSE compensated buck converter and its transient response are given and analysed by using some of the results from [20][21][22][23][24][25][26]. The optimal design procedure and piecewise adjustment method are also given.…”