Digital FIR filters for high speed PRML disk read channels

Pearson, D.J.; Reynolds, Scott; Megdanis, A.C.; Gowda, S.; Wrenner, K.R.; Immediato, M.; Galbraith, Rick; Shin, Hyunho

doi:10.1109/4.482200

Cited by 20 publications

(6 citation statements)

References 3 publications

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“…A particular approach that is very well-suited for a high performance implementation is the distributed arithmetic architecture [8]. This approach does not use multiplier units.…”

Section: Implementation: Distributed Arithmetic Stylementioning

confidence: 99%

“…To further reduce the table size in half, a data representation scheme is used that makes the table symmetric. In particular, the signed-digit offset binary notation [8] is used, in which the symbols "0" and "1" stand for negative and positive exponents of 2. For example, in this notation, the 4-bit number "1001" stands for the value 8 − 4 − 2 + 1 = 3.…”

Section: Implementation: Distributed Arithmetic Stylementioning

confidence: 99%

“…Figure 6 shows the top-level architecture of the digital filter. The filter is a 10-tap 6-bit FIR filter using the distributed arithmetic architecture [8]. The figure gives a detailed view of one bit slice; as indicated, there are actually six such bit slices, stacked on top of each other.…”

Section: Timing Constraintsmentioning

confidence: 99%

“…Finally, a second optimization is used: a signed-digit offset binary notation [8] is used to represent table entries and addresses, which enables the separation of the sign-bit from each address, further shortening the addresses to 4-bit words (see Section 2.1). As a result, the table size is dramatically reduced: two tables with only 16 (= 2 4 ) entries each are needed, as opposed to one table with 1024 (= 2 10 ) entries.…”

Section: The Synchronous Input Portionmentioning

confidence: 99%

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An Adaptively Pipelined Mixed Synchronous-Asynchronous Digital FIR Filter Chip Operating at 1.3 Gigahertz

Singh

Tierno

Rylyakov

et al. 2010

IEEE Trans. VLSI Syst.

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A high-throughput low-latency digital finite impulse response (FIR) filter has been designed for use in partialresponse maximum-likelihood (PRML) read channels of modern disk drives. The filter is a hybrid synchronousasynchronous design. The speed critical portion of the filter is designed as a high-performance asynchronous pipeline, sandwiched between synchronous input and output portions, making it possible for the entire filter to be dropped into a clocked environment. A novel feature of the filter is that the degree of pipelining is dynamically variable, depending upon the input data rate. This feature is critical in obtaining a very low filter latency throughout the range of operating frequencies. The filter was fabricated in a 0.18µ CMOS process. Resulting chips were fully functional over a wide range of supply voltages, and exhibited throughputs of over 1.3 Giga items/second, and latencies as low as four clock cycles. The internal asynchronous pipeline was estimated to be capable of significantly higher throughputs, around 1.8 Giga items/second. With these performance metrics, the filter has better performance than that reported for existing digital read channel filters.

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“…A particular approach that is very well-suited for a high performance implementation is the distributed arithmetic architecture [8]. This approach does not use multiplier units.…”

Section: Implementation: Distributed Arithmetic Stylementioning

confidence: 99%

Section: Implementation: Distributed Arithmetic Stylementioning

confidence: 99%

Section: Timing Constraintsmentioning

confidence: 99%

Section: The Synchronous Input Portionmentioning

confidence: 99%

See 2 more Smart Citations

An Adaptively Pipelined Mixed Synchronous-Asynchronous Digital FIR Filter Chip Operating at 1.3 Gigahertz

Singh

Tierno

Rylyakov

et al. 2010

IEEE Trans. VLSI Syst.

View full text Add to dashboard Cite

show abstract

“…Recently, because of the increasing demand for video-signal processing and transmission, high-speed and high-order FIR filters have frequently been used to perform adaptive pulse shaping and signal equalization on the received data in realtime, e.g., ghost cancellation [1], [2], source coding, equalizer, Partial-Response Maximum Likelihood (PRML), and channel equalization [3]. Signal processing algorithms often require a substantial amount of floating-point (or fixed-point) computations to be performed at real-time or near real-time speeds.…”

Section: Introductionmentioning

confidence: 99%

A High-Performance 8-Tap FIR Filter Using Logarithmic Number System

Sun

Kim

2011

2011 IEEE International Conference on Communications (ICC)

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This paper presents an approach to implement a high-performance 8-tap digital FIR (Finite Impulse Response) filter using the Logarithmic Number System. In the past, FIR filters were implemented by a conventional number system; their speed was limited because of the multiply-accumulate operations. We realize a fast FIR filter by utilizing the Logarithmic Number System, which allows a simple implementation of multiplication using a fixed-point adder. And the serious demerit of Logarithmic Number System's algorithm, conversions to and from the conventional number representations, is effectively overcome by pipelining to reduce the delay and complexity of the filter. The critical path was reduced from a multiply-accumulate operation to an add operation. Our FIR filter can operate at 1.3 GHz under the condition of 1.2 V power supply using the SMIC 0.13 µm CMOS technology, and requires 27% less area than the original FIR filter.

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Design of high throughput asynchronous FIR filter using gate level pipelined multipliers and adders

Sravani

Rao

2020

Circuit Theory & Apps

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SummaryThis work presents the design of an asynchronous digital finite impulse response (FIR) filter suitable for high‐performance partial response maximum likelihood (PRML) read channel ICs. A high throughput, low latency FIR filter is the basic requirement for the equalization process in read channels. To achieve the enhancement in speed and reduction in latency of the FIR filter, its computational units are deeply pipelined using high‐capacity hybrid (HC‐hybrid) logic pipeline method. The designed FIR filter has been simulated using UMC‐180 nm and UMC‐65 nm technologies. Simulation results show that the asynchronous digital FIR filter can operate up to a throughput of 1.17 Giga items/s in 180 nm and 2.3 Giga items/s in 65 nm technology yet with the latency in the order of ns.

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Digital FIR filters for high speed PRML disk read channels

Cited by 20 publications

References 3 publications

An Adaptively Pipelined Mixed Synchronous-Asynchronous Digital FIR Filter Chip Operating at 1.3 Gigahertz

An Adaptively Pipelined Mixed Synchronous-Asynchronous Digital FIR Filter Chip Operating at 1.3 Gigahertz

A High-Performance 8-Tap FIR Filter Using Logarithmic Number System

Design of high throughput asynchronous FIR filter using gate level pipelined multipliers and adders

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