A High-Performance 8-Tap FIR Filter Using Logarithmic Number System

Sun, Yan; Kim, Min‐Sik

doi:10.1109/icc.2011.5962827

Cited by 7 publications

(4 citation statements)

References 11 publications

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“…where y(n) denotes the current filter outcomes, y(n−k) denotes the present or previous filter intakes, a k denotes the feed-forward parameters related to the filter zeros, b k denotes the feedback coefficient relating to the filter pole, and N defines the orders [22,23]. Digital filters are categorized primarily into two types: (1) finite impulse response (FIR) or non-recursive filters and (2) infinite impulse response (IIR) or recursive filters.…”

Section: Fir Filter As a Loop Filter (Lf) Used In Adpll'smentioning

confidence: 99%

FPGA implantations of TRNG architecture using ADPLL based on FIR filter as a loop filter

Meitei

Kumar

2022

SN Appl. Sci.

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This article describes about the design, implementation, and analysis of a true random number generator (TRNG) employing an all-digital phase-locked loop (ADPLL) based on a finite impulse response (FIR) filter as the digital loop filter and implemented on the Artix 7(XC7A35T-CPG236-1) field programmable gate array (FPGA) board using the Xilinx Vivado v.2015.2 design suite. The coefficients of a 3rd-order broadcast low-pass digital FIR filter are computed using the Keiser window method. The MATLAB-FDA tool is used to calculate the filter coefficient. After reducing the bias in the sequence using the XOR-corrector post-processing approach, the suggested ADPLL-based TRNG designs created an unbiased stochastic random number with an overall throughput of 200 Mbps for both designs. The first proposed FIR-ADPLL-based TRNG design (FAT-1) consumes 0.072 W of power, whereas the second proposed FIR-ADPLL-based TRNG design (FAT-2) consumes 0.074 W. The resulting bitstream is verified for randomness using national institute of standards and technology (NIST) test following post-processing. Digital storage oscilloscope (DSO) is interfaced to the Artrix-7 FPGA board in order to capture the TRNG output waveforms. Both the proposed FIR-based ADPLL-TRNG designs passed the NIST SP 800-22 test, indicating that they are well-suited for a variety of industrial applications, including network security, cybersecurity, banking security, smart cards, radio-frequency identification tags, Internet of Things, and Industrial Internet of Things.

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Section: Fir Filter As a Loop Filter (Lf) Used In Adpll'smentioning

confidence: 99%

FPGA implantations of TRNG architecture using ADPLL based on FIR filter as a loop filter

Meitei

Kumar

2022

SN Appl. Sci.

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“…Many handheld and portable signal-processing devices are parts of our daily life. The Digital signal processor and image processor have required accurate and efficient arithmetic operations for performing fast and efficient real-time applications [1][2][3][4][5][6][7][8][9]. As its well-known thing, that multiplier is the most utilized component in arithmetic operations.…”

Section: Introductionmentioning

confidence: 99%

An Efficient Antilogarithmic Converter by Using Correction Scheme for DSP Processor

Nandan¹

2020

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Digital Signal Processing (DSP) applications demand error-free and compact hardware architecture of arithmetic operations. A logarithmic operation provides an efficient option in place of binary arithmetic. In this paper, it is suggested that 11-region and 17-region error correction schemes for developing an efficient antilogarithm converter. It is used for developing the most accurate and compact logarithm multiplier which is used in the DSP processor. Implementations of reported and proposed designs are investigate based on accuracy and hardware overhead and it found outperform in comparisons of previously reported designs. The proposed 11-region converter involves 61% less Area Delay Product (ADP) and 49.82% less energy in comparisons of the reported 11-region antilogarithmic converter and 17-region converter involves 48.02% less ADP and 32.53% less energy in comparisons of the reported 14-region antilogarithmic converter. The proposed antilogarithmic converter achieves 1.697% and 1.084% error for 11-region and 17-region designs respectively than of reported designs of 1.876% and 1.351% for 11-region and 17region respectively.

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“…With LNS reducing multiplication to an addition, it finds application in low power signal processing systems, including digital filters [13,[17][18][19][20][21][22][23]. In [18,19] LNS has also been proposed to reduce power dissipation in hearing aid devices [24], subband coding [25], and video processing [26].…”

Section: Introductionmentioning

confidence: 99%

Design of Finite Word Length Linear-Phase FIR Filters in the Logarithmic Number System Domain

Alam

Gustafsson

2014

VLSI Design

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Logarithmic number system (LNS) is an attractive alternative to realize finite-length impulse response filters because of multiplication in the linear domain being only addition in the logarithmic domain. In the literature, linear coefficients are directly replaced by the logarithmic equivalent. In this paper, an approach to directly optimize the finite word length coefficients in the LNS domain is proposed. This branch and bound algorithm is implemented based on LNS integers and several different branching strategies are proposed and evaluated. Optimal coefficients in the minimax sense are obtained and compared with the traditional finite word length representation in the linear domain as well as using rounding. Results show that the proposed method naturally provides smaller approximation error compared to rounding. Furthermore, they provide insights into finite word length properties of FIR filters coefficients in the LNS domain and show that LNS FIR filters typically provide a better approximation error compared to a standard FIR filter.

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A High-Performance 8-Tap FIR Filter Using Logarithmic Number System

Cited by 7 publications

References 11 publications

FPGA implantations of TRNG architecture using ADPLL based on FIR filter as a loop filter

FPGA implantations of TRNG architecture using ADPLL based on FIR filter as a loop filter

An Efficient Antilogarithmic Converter by Using Correction Scheme for DSP Processor

Design of Finite Word Length Linear-Phase FIR Filters in the Logarithmic Number System Domain

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