Digital delay locked loop‐based frequency synthesiser for Digital Video Broadcasting‐Terrestrial receivers

Gholami, Mohammad; Rahimpour, Hamid; Ardeshir, Gholamreza; Naimi, Hossein Miar

doi:10.1049/iet-cds.2013.0169

Cited by 11 publications

(3 citation statements)

References 24 publications

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“…On the contrary, since the noise from VCDL is located behind the filter capacitor, so it presents a highpass behaviour, allowing the extension of the loop bandwidth for suppressing high-frequency noise. Particularly, since the reference clock noise is almost simultaneously injected to the PD and the VCDL, it exhibits nearly all pass characteristics, indicating that all the clock jitter is fully transported to the output; therefore, a highquality reference clock is definitely beneficial to depress the output noise [12][13][14][15]. In practical, the baseband noise dominant in the low-and medium-frequency region should be seriously restricted, so the upper bound of loop bandwidth is limited for reducing the output jitters mainly coming from PD and CP noises, while the low limit of loop bandwidth is restricted for reducing the output jitters mainly coming from VCDL and input clock noise.…”

Section: Proposed Compact Dll-tdc Architecturementioning

confidence: 99%

Low‐jitter DLL applied for two‐segment TDC

Zhang

Zhao

et al. 2017

IET Circuits, Devices & Systems

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A low-jitter delay-locked loop (DLL) for high-resolution time-to-digital converter (TDC) is proposed in this study. The generated high accurate and low-jitter outputs with uniformly distributed multiphase clocks directly from the voltage-controlled delay line (VCDL) in DLL are applied to two-segment TDC. For reducing the static phase offset in locked state, the charge pump with interior feedback loop is used to achieve a better current matching between the charging and discharging currents. An improved phase detector as well as a differential VCDL excellent in linearity property and noise suppression is utilised for reducing the output clock jitter. Fabricated by TSMC 0.35 μm complementary metal-oxide-semiconductor process, the measurement results show that DLL's frequency locking range is 60-240 MHz, the output clock jitters at 125 MHz are 3.6 ps for root mean square and 35.07 ps for peak-to-peak. By clock period counting and eight-phase discrimination, the resolution of <1 ns and maximum range of around 1 μs as well as the differential non-linearity <0.68 LSB and the integration non-linearity within −0.97 to 1.24 LSB are obtained for two-segment TDC.

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Section: Proposed Compact Dll-tdc Architecturementioning

confidence: 99%

Low‐jitter DLL applied for two‐segment TDC

Zhang

Zhao

et al. 2017

IET Circuits, Devices & Systems

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“…They are unavoidable parts in communication systems. Due to the better jitter performance of DLLs, they are used more than PLLs when minimizing of jitter is important [5,6]. Conventional DLLs are first order system, hence they are inherently stable.…”

Section: Introductionmentioning

confidence: 99%

Dual Phase Detector Based Delay Locked Loop for High Speed Applications

Gholami

Ardeshir

2014

IJE

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In this paper a new architecture for delay locked loops is proposed. Static phase offset and reset path delay are the most important problems in phase-frequency detectors (PFD). The proposed structure decreases the jitter resulted from PFD by switching two PFDs. In this new architecture, a conventional PFD is used before locking of DLL to decrease the amount of phase difference between input and output of the DLL. Near locking, an XOR gate is used to act as a PFD which makes the DLL locks with less jitter. Also, the reset path time and glitch are decreased by using the XOR gate. The proposed architecture has been designed in TSMC 0.18um CMOS Technology. The simulation results support the theoretical design aspects.

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“…Jitter, power consumption and phase noise are important parameters and when there is no need to generate fractional mu lt iple of reference frequency, DLL is used instead of PLL because of its better performance. In addition, DLLs are widely used in dig ital co mmun ication circuits [9,10,11]. In design of frequency multiplier and clock and data recovery circuits, jitter is one of the most important parameters.…”

Section: Introductionmentioning

confidence: 99%

A Noise and Mismatches of Delay Cells and Their Effects on DLLs

Gholami

Ardeshir²,

Naimi³

2014

IJISA

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Jitter is one of the most important parameters in design of delay locked loop (DLL) based frequency synthesizer. In this paper noise and mis matches of conventional delay cells which are mainly used in the DLLs architecture are introduced completely. First, time domain equations related to noise and mis matches of conventional delay cells are reported. Then, these equations are used to calculate jitter of DLL due to mis match and noise of delay cells. At last closed form equations are obtained which can be used in the designing of low jitter DLLs. To validate these equations, a conventional DLL is designed in TSM C 0.18um CMOS Technology.

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Digital delay locked loop‐based frequency synthesiser for Digital Video Broadcasting‐Terrestrial receivers

Cited by 11 publications

References 24 publications

Low‐jitter DLL applied for two‐segment TDC

Low‐jitter DLL applied for two‐segment TDC

Dual Phase Detector Based Delay Locked Loop for High Speed Applications

A Noise and Mismatches of Delay Cells and Their Effects on DLLs

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