Dual Phase Detector Based Delay Locked Loop for High Speed Applications

Abstract

In this paper a new architecture for delay locked loops is proposed. Static phase offset and reset path delay are the most important problems in phase-frequency detectors (PFD). The proposed structure decreases the jitter resulted from PFD by switching two PFDs. In this new architecture, a conventional PFD is used before locking of DLL to decrease the amount of phase difference between input and output of the DLL. Near locking, an XOR gate is used to act as a PFD which makes the DLL locks with less jitter. Also, the reset path time and glitch are decreased by using the XOR gate. The proposed architecture has been designed in TSMC 0.18um CMOS Technology. The simulation results support the theoretical design aspects.

Modified Second Order Generalized Integrator-frequency Locked Loop Grid Synchronization for Single Phase Grid tied System Tuning and Experimentation Assessment

“…A new version of the band-pass SOGI-FLL (Figure 5) filter [17][18][19] designated as MSOGI-FLL can be proposed by including the DSC operator. A grid signal polluted with a DC-offset, MSOGI transfer functions is represented as follows for comprehension purposes: In order to filter out low and high-frequency components in the input signals, gain k must be properly tuned.…”