A Noise and Mismatches of Delay Cells and Their Effects on DLLs

Abstract

Jitter is one of the most important parameters in design of delay locked loop (DLL) based frequency synthesizer. In this paper noise and mis matches of conventional delay cells which are mainly used in the DLLs architecture are introduced completely. First, time domain equations related to noise and mis matches of conventional delay cells are reported. Then, these equations are used to calculate jitter of DLL due to mis match and noise of delay cells. At last closed form equations are obtained which can be used in the designing of low jitter DLLs. To validate these equations, a conventional DLL is designed in TSM C 0.18um CMOS Technology.

Design of Low Power Sequential Circuit by using Adiabatic Techniques

“…But in CMOS logic design, charge flow in the circuit is studied and many methods can be used for minimizing power dissipation in basic CMOS design like: reducing the power supply and switching activities. A combination of above all is important in portable systems which have some common issues such as weight, size and life of battery [2,4,27].…”