Differential Cascode Voltage Switch (DCVS) Strategies by CNTFET Technology for Standard Ternary Logic

Mirzaee, Reza Faghih; Nikoubin, Tooraj; Navi, Keivan; Hashemipour, Omid

doi:10.1016/j.mejo.2013.08.010

Cited by 23 publications

(10 citation statements)

References 36 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…1. The static DCVS-based standard ternary gates (Inverter/ Buffer, AND/NAND, OR/NOR), which are fundamental components of every arithmetic or logic units, are proposed with the use of CNTFET technology [12]. Minority function is utilized in the voting systems for decision making and also it is used in data mining [13].…”

Section: Introductionmentioning

confidence: 99%

Comparative Analysis of CNTFET and CMOS Logic based Arithmetic Logic Unit

Kandasamy¹,

Nagarjuna²,

Vijay³

2017

J. Nano- Electron. Phys.

View full text Add to dashboard Cite

This paper proposes the novel low power and area efficient ALU (Arithmetic and Logic Unit) using adder and multiplexers. The adder and multiplexer are realized by using CNTFET (Carbon Nano Tube Field Effect Transistor) A verilog model of MOSFET (Metal Oxide Semiconductor Field Effect Transistor) in cadence spice software. The proposed ALU is simulated using Monte carlo simulation at 0.9 sub threshold voltage tested with 45 nm technology for the measurement of power and transistor counts. The power consumption of CNTFET based ALU is found to be 45.67 % better than the existing technologies.

show abstract

Section: Introductionmentioning

confidence: 99%

Comparative Analysis of CNTFET and CMOS Logic based Arithmetic Logic Unit

Kandasamy¹,

Nagarjuna²,

Vijay³

2017

J. Nano- Electron. Phys.

View full text Add to dashboard Cite

show abstract

“…CNTFET is the most promising successor technology to the conventional silicon-based devices because of its infrastructural and operational similarities with complementary metal-oxide-semiconductor (CMOS) [8]. Recently, some CNTFET-based circuits have been presented in the literature for multi-V t structures [8][9][10][11]. A single-walled carbon nanotube (SWCNT) can be either a conductor or a semiconductor according to its chiral numbers (n 1 , n 2 ).…”

Section: Introductionmentioning

confidence: 99%

“…The main property of CNTFETs is the capability of adjusting the desired threshold voltage by changing the diameter of the nanotubes. As a result, it makes them appropriate for designing multi-V t circuits [11]. The threshold voltage of a CNTFET is approximated as the half bandgap and specified by the following equation [12,13]…”

Section: Introductionmentioning

confidence: 99%

A new approach for designing compressors with a new hardware‐friendly mathematical method for multi‐input XOR gates

Daliri

Navi

Mirzaee

et al. 2017

IET Circuits, Devices & Systems

Self Cite

View full text Add to dashboard Cite

This study presents a new scalable mathematical approach for designing compressors with any arbitrary number of inputs using multi-input threshold gates, behaving as exclusive-OR (XOR). This study relates the theoretical concept to hardware implementation. The methodology is exploited for 3:2, 7:3, and 15:4 compressors, and then implemented by using input capacitors (or resistors) and threshold detectors. The transistor-level realisation of 3:2 and 7:3 compressors is simulated by using Synopsys HSPICE and 32 nm Carbon Nanotube Field Effect Transistors technology. The proposed methodology benefits from the parallel operation of threshold detectors. Therefore, by increasing the number of inputs, the delay parameter does not increase dramatically. The layout views are also provided in order to be able to compare area for the 3:2 compressors with both capacitor and resistor networks.

show abstract

“…Differential Cascode Voltage Switch Logic (DCVSL) [6] is a static style which is beneficial from circuit delay, layout density, logic flexibility, and power consumption. The DCVSL has been employed to develop various circuits for fault tolerance [7], ternary logic [8], micro pipelining [9], delay cell [10], ring oscillator [11], capacitor neutralization [12], and so forth. It is well known that static logic styles suffer from high power consumption when output switches its logic state, a situation which worsens with increasing clock frequencies.…”

Section: Introductionmentioning

confidence: 99%

On Improving the Performance of Dynamic DCVSL Circuits

Bajpai

Pandey

Gupta

et al. 2017

Journal of Electrical and Computer Engineering

View full text Add to dashboard Cite

This contribution aims at improving the performance of Dynamic Differential Cascode Voltage Switch Logic (Dy-DCVSL) and Enhanced Dynamic Differential Cascode Voltage Switch Logic (EDCVSL) and suggests three architectures for the same. The first architecture uses transmission gates (TG) to reduce the logic tree depth and width, which results in speed improvement. As leakage is a dominant issue in lower technology nodes, the second architecture is proposed by adapting the leakage control technique (LECTOR) in Dy-DCVSL and EDCVSL. The third proposed architecture combines features of both the first and the second architectures. The operation of the proposed architectures has been verified through extensive simulations with different CMOS submicron technology nodes (90 nm, 65 nm, and 45 nm). The delay of the gates based on the first architecture remains almost the same for different functionalities. It is also observed that Dy-DCVSL gates are 1.6 to 1.4 times faster than their conventional counterpart. The gates based on the second architecture show a maximum of 74.3% leakage power reduction. Also, it is observed that the percentage of reduction in leakage power increases with technology scaling. Lastly, the gates based on the third architecture achieve similar leakage power reduction values to the second one but are not able to exhibit the same speed advantage as achieved with the first architecture.

show abstract

Differential Cascode Voltage Switch (DCVS) Strategies by CNTFET Technology for Standard Ternary Logic

Cited by 23 publications

References 36 publications

Comparative Analysis of CNTFET and CMOS Logic based Arithmetic Logic Unit

Comparative Analysis of CNTFET and CMOS Logic based Arithmetic Logic Unit

A new approach for designing compressors with a new hardware‐friendly mathematical method for multi‐input XOR gates

On Improving the Performance of Dynamic DCVSL Circuits

Contact Info

Product

Resources

About