Device performance in a fully functional 800MHz DDR3 spin torque magnetic random access memory

Janesky, J.; Rizzo, Nicholas D.; Houssameddine, D.; Whig, R.; Mancoff, F. B.; DeHerrera, M.; Sun, J. J.; Schneider, Michael L.; Chia, Hao-Chung; Aggarwal, S.; Nagel, K.; Deshpande, S.; Andre, T.; Alam, Syed Q.; Tan, Charles; Slaughter, J. M.; Hellmold, S.; Lopresti, Philip V.

doi:10.1109/imw.2013.6582086

Cited by 9 publications

(8 citation statements)

References 11 publications

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“…目前已有诸多的STT-MRAM测试芯片和商用产品问世. 表2 [11,[111][112][113][114][115][116][117][118][119][120][121][122][123][124][125][126][127][128] 列举了近年来学术界和工业界在该领表 2 近年来的STT-MRAM芯片性能指标 Univ Toronto/Fujitsu Lab [111] 16 Kbit 130 cell: 5.525 R: 9, W: 9-10 a) W: 0.4-0.87 mA 2010 Toshiba [112] 64 Mbit 65 cell: 0.3584, Die: 47.124 30 R: 10 μA, W: 49 μA 2010 Hynix/Grandis [113] 64 Mbit 54 Cell: 0.041 R: <20 W: 140 μA…”

Section: 随着磁隧道结制备工艺的改进和电路性能的优化unclassified

“…Hitachi/Univ Tohoku [114] 32 Mbit 150 cell: 1, chip: 94.83 R: 32, W: 40 W: 300 μA 2010 IBM [115] 4 Kbit array -W: 50 W:~200 μA 2011 Qualcomm [116] 1 Mbit 45 cell: 0.1026, chip: 0.27 R: 10 -2012 Everspin [32,117] 64 Mbit 90 -10~50 -2013 TSMC [118] 1 Mbit 40 macro: 0.56 mm 2 R: 10 W: 281-283 μA 2013 NEC/Univ Tohoku [119] 1 Toshiba [121] 512 Kbit 65 cell: 0.504 8 R: 4 mW, W: 15 mW 2013 Toshiba [122] 1 Mbit 65 cell: 0.45 R: 4, W: 4 R: 0.142 nJ, W: 0.372 nJ 2013 Infineon/TUM [123] 8 Mbit 40 -R: 23 -2014 TDK-Headway [124] 8 Mbit 90 cell: 0.4 W: <5, R: 4 -2015 IBM [125] 4 Kbit array -W: 20-50 -…”

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confidence: 99%

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Recent progresses in spin transfer torque-based magnetoresistive random access memory (STT-MRAM)

Zhao¹,

Wang²,

Peng³

et al. 2016

Sci. Sin.-Phys. Mech. Astron.

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Section: 随着磁隧道结制备工艺的改进和电路性能的优化unclassified

mentioning

confidence: 99%

Recent progresses in spin transfer torque-based magnetoresistive random access memory (STT-MRAM)

Zhao¹,

Wang²,

Peng³

et al. 2016

Sci. Sin.-Phys. Mech. Astron.

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“…The endurance of existing PCM implementations is in the range of c 2015 Information Processing Society of Japan Table 1 Comparison of traditional memory and NVM technologies [13], [14], [15], [16], [17], [18]. [31], which transfers data at a speed comparable to current DDR3-1600 DRAM.…”

Section: Rerammentioning

confidence: 99%

“…For example, we can implement the off-chip NVM main memory as dual in-line memory modules (DIMMs), which is compatible to the commodity off-chip DRAM implementations [32]. Most NVM technologies are not compatible with CMOS technology, which is the traditional technology used to implement the processor cores and caches.…”

Section: Replacing Traditional Memory Technologies With Nvmsmentioning

confidence: 99%

Memory and Storage System Design with Nonvolatile Memory Technologies

Zhao

Chi

et al. 2015

IPSJ Transactions on System LSI Design Methodology

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Abstract:The memory and storage system, including processor caches, main memory, and storage, is an important component of various computer systems. The memory hierarchy is becoming a fundamental performance and energy bottleneck, due to the widening gap between the increasing bandwidth and energy demands of modern applications and the limited performance and energy efficiency provided by traditional memory technologies. As a result, computer architects are facing significant challenges in developing high-performance, energy-efficient, and reliable memory hierarchies. New byte-addressable nonvolatile memories (NVMs) are emerging with unique properties that are likely to open doors to novel memory hierarchy designs to tackle the challenges. However, substantial advancements in redesigning the existing memory and storage organizations are needed to realize their full potential. This article reviews recent innovations in rearchitecting the memory and storage system with NVMs, producing high-performance, energy-efficient, and scalable computer designs.

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“…The fast access speed and good scalability potentially help improve the TCAM density and enhance the searching speed as well. Among various NVMs, magnetic tunneling junction (MTJ) could be one of the best candidates for TCAM design considering its technology readiness and commercialization status [5].…”

Section: Introductionmentioning

confidence: 99%

A High-Speed Robust NVM-TCAM Design Using Body Bias Feedback

Yan

Zhang

et al. 2015

Proceedings of the 25th Edition on Great Lakes Symposium on VLSI

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As manufacture process scales down rapidly, the design of ternary content-addressable memory (TCAM) requiring high storage density, fast access speed and low power consumption becomes very challenging. In recent years, many novel TCAM designs have been inspired by the research on emerging nonvolatile memory technologies, such as magnetic tunneling junction (MTJ), phase change memory (PCM), and memristor. These designs store a data as the resistive variable of a nonvolatile device, which usually results in limited sensing margin and therefore constrains the searching speed of TCAM architecture severely. To further enhance the performance and robustness of TCAMs, we proposed two novel cell designs that utilize MTJs as data storage units-the symmetrical dual-N structure and the asymmetrical P-N scheme. In both designs, a body bias feedback circuit is integrated to enlarge the sensing margins. Compared with an existing MTJ-based TCAM structure, the tolerance in gate voltage variation of the symmetrical dua-N (asymmetrical P-N) scheme can significantly improve 59.5% (21.2%). The latency and the dynamic energy consumption in one searching operation at the word length of 256 bits are merely 590.35ps (97.89ps) and 65.05f J/bit (36.85f J/bit), not even mentioning that the use of nonvolatile MTJ devices avoids unnecessary leakage power consumption.

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Device performance in a fully functional 800MHz DDR3 spin torque magnetic random access memory

Cited by 9 publications

References 11 publications

Recent progresses in spin transfer torque-based magnetoresistive random access memory (STT-MRAM)

Recent progresses in spin transfer torque-based magnetoresistive random access memory (STT-MRAM)

Memory and Storage System Design with Nonvolatile Memory Technologies

A High-Speed Robust NVM-TCAM Design Using Body Bias Feedback

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