Device design of single-gated feedback field-effect transistors to achieve latch-up behaviors with high current gains

NAND and NOR logic-in-memory comprising silicon nanowire feedback field-effect transistors

“…The operation principle of the p - and n -FBFETs is based on a positive feedback loop mechanism in the channel regions 29 – 31 . The FBFETs consisting of p + – n + – p + – n + regions have two potential barriers in the channel regions, and the potential barrier heights are controlled by the presence or absence of charge carriers in the potential well.…”

“…In this study, we propose a NAND and NOR LIM composed of silicon nanowire (SiNW) feedback field-effect transistors (FBFETs) to verify universal gate functions, where the configuration of the SiNW FBFETs maintains conventional CMOS logic gates. The SiNW FBFETs utilized in the LIM have demonstrated near-zero subthreshold swings ( SS ), high speed, low operating voltage, and quasi-nonvolatile memory characteristics based on the positive feedback loop mechanism 29 – 31 . The LIM exhibits a high processing speed close to that of SRAM and DRAM (< 5 ns), ultra-low standby power while storing the data, retention characteristics that will retain certain computational logic states without power supply, and relatively low operating voltage (≤ 2.5 V) compared to flash memory.…”

“…The proposed LIM has excellent gate controllability of charge carriers in the silicon channel and has a simple fabrication process by CMOS-compatible top-down technology 32 , 33 . The FBFETs could be produced using commercially available fabrication processes of conventional GAA SiNWs, and our LIM could be implemented by arranging the FBFETs as CMOS logic circuit 31 . Thus, it is feasible that our LIM is made in commercially available fabrication processes 34 .…”

Neural oscillation of single silicon nanowire neuron device with no external bias voltage

“…The spike and reset mechanisms of the neuron device enabling information transfer for synapse devices are explained using an equivalent circuit. The equivalent circuit of our neuron device consists of coupled bipolar junction transistors (BJTs) and an n-channel metal-oxide- semiconductor field-effect transistor (MOSFET) 27 , as shown in Fig. 3 b, c. The input voltage, output spike voltage ( V Spike ), recombination rate, and electron density during the LIF operation are plotted as functions of time in Fig.…”

Simulation studies on electrical characteristics of silicon nanowire feedback field-effect transistors with interface trap charges

“…Figure 2 c and f show the I DS − V GS transfer curve depicting the latch-up/down phenomena and on/off state under different three gate voltages. These voltage differences between the latch-up voltage ( V Latch-up ) and latch-down voltage ( V Latch-down ) are defined as the memory window for memory operations 15 . In the following sections, we analyze how the presence of ITCs affects the positive feedback mechanisms on the n - and p -FBFETs.…”