Device Design Engineering for Optimum Analog/RF Performance of Nanoscale DG MOSFETs

Temperature dependence inflection point in Ultra-Thin Si directly on Insulator (SDOI) MOSFETs: An influence to key performance metrics

“…So, from the figure, high gain can be obtained for high temperatures. The intrinsic gain can also be expressed as [16]:…”

“…It also offers a very good option for analog and RF applications [15][16][17][18]. So far, very little work has been reported in the literature which prompted the authors for further investigation of the inflection point due to wide temperature for multi-gate technology.…”

Resolving the bias point for wide range of temperature applications in High-k/Metal Gate nanoscale DG-MOSFET

“…The Double Gate (DG) MOSFET fabricated on SOI wafers is one of the most promising candidates due to its attractive features of low leakage currents, high current drivability (I on ) & transconductance (g m ), reduced short channel effects (SCEs), steeper subthreshold slopes, and suppression of latch-up phenomenon [7][8][9][10], and also it is a very good option for analog applications [11][12][13][14]. Hardly any work has been reported to investigate the ZTC point for multi-gate technology.…”

Analog and radio-frequency (RF) performance evaluation of fully-depleted (FD) recessed-source/drain (Re-S/D) SOI MOSFETs

“…FD SOI MOSFETs have demonstrated tremendous potential for analog and radio-frequency (RF) applications in sub 50 nm technology node with very high cut-off frequency (f T ) (up to 300 GHz) and maximum frequency of oscillation (f max ) (up to 1000 GHz) [15][16][17][18][19][20][21][22][23][24], which make SOI MOSFET an attractive candidate for systems-on-a-chip (SOC) applications. A number of attempts have been made to further optimize the analog and RF performance of the SOI MOSFETs with device engineering [15][16][17][18][19][20][21][22][23][24].…”

“…A number of attempts have been made to further optimize the analog and RF performance of the SOI MOSFETs with device engineering [15][16][17][18][19][20][21][22][23][24]. Kranti et al [15] had examined the analog/RF performance of SOI MOSFETs with underlap channel for low voltage applications.…”