Device characteristics of a 30-V-class thin-film SOI power MOSFET

Hot carrier effect of a scaled thin-film SOI power MOSFET under constant drain electric field

“…The degradation rate of the device with channel length of 0.5 m is higher than that of 1.0 μm despite the same electric field. Degradation pronounced at an early stage, and it is saturated [3]. There are two kinds of degradation of onresistance by hot carrier injection [3].…”

“…Degradation pronounced at an early stage, and it is saturated [3]. There are two kinds of degradation of onresistance by hot carrier injection [3]. The one is degradation near threshold voltage.…”

“…1) is how to improve their high-frequency switching performance. This have been actively studied by reducing the on-resistance and parasitic capacitance [3]. The one of the most effective ways to do these is to shrink the channel length with keeping electric field of the drift region.…”

170V Super Junction - LDMOST in a 0.5 μm commercial CMOS/SOS technology

“…These compensated regions are mandated by the technology design rules of the process used, in which the minimum width of the pillars is 0.8 Fm (larger than what is needed to deplete the pillars effectively). P+ contacts are inserted in the source diffusion region to tie the channel and the p-pillars to ground [3] to suppress parasitic bipolar action and provide a good ohmic contact which acts as a sinWsource for camers originating in the pillars during device switching [4]. In the layout, a blocking masking layer (SDBLOCK) is included to mask the self-aligned LDD ion-implantations in the drift region.…”

Novel techniques for reducing self-heating effects in silicon-on-insulator power devices

“…The main parameters correspond to the 30 V LDMOS device integrated on ThinFilm SO1 substrates, proposed by Matsumoto et al[12]. Studies on RF applications of this LDMOS structure have shown that an undesired self-heating appears when increasing the operating frequency [ 131, which can…”