170V Super Junction - LDMOST in a 0.5 μm commercial CMOS/SOS technology

Abstract

This paper reports on an experimental 17OV SuperJunction -LDMOST (SJ-LDMOST) implemented in a 0.5 Fm CMOSlSOS technology developed primarily for low voltage RF and mixed signal applications. An experimental SJ-LDMOST with a drift region length of IO p n and a 'drift region pillar doping concentration of -2 x I O "~m -~ exhibits a breakdown voltage of 170V. The high average lateral electric field of 17V/pm implies that (near) charge compensation, between the altemating polarity pillars, has been achieved. 3D device simulations predict that the silicon limit in conventional LDMOSTs can be broken when the aspect ratio of pillar height to width exceeds 1.

A Review of Super Junction LDMOS

“…Simulation results indicate that the BV of the proposed device with the drift length of 10 μm is 223V. Figure 19 shows SJ-LDMOS on silicon-on-sapphire (SOS) substrate [36][37][38]. The structure can eliminate the SAD effect.…”

A superjunction LDMOST with a floating oppositely doped buried layer in substrate

“…However, when the SJ concept is introduced to lateral DMOS (LDMOST), the charges between the SJ n-and p-pillars are no more compensated each other. This is substrate-assisted-depletion effect [3] and the blocking capability is deteriorated severely [1,4]. Several technologies and structures have been proposed to compensate the depleted SJ charges by vertical pn junction, such as the unbalanced SJ-LDMOST [5], the SJ/RESURF LDMOST [6], the SLOP-LDMOST [7], the buffered SJ-LDMOST [8].…”

Realizing high voltage SJ-LDMOS with non-uniform N-buried layer

“…Lateral double-diffused MOSFETs (LDMOST) based on the super junction (SJ) concept were recently proposed to further improve the trade-off characteristics between the breakdown voltage (BV) and the on-resistance (R on ) which has always been a major issue in the design of power device [1][2][3][4][5][6]. The SJ concept is based on achieving charge compensation in the off-state, in a set of alternating and heavily doped n and p pillars comprising the drift region of the device.…”

“…To overcome this, it is possible to use silicon on sapphire (SOS) technology as a dielectric substrate. In that case, the interaction between the substrate and the SJ pillars is eliminated completely [2,3]. Unfortunately, the use of a sapphire substrate is expensive and not mainstream silicon technology.…”