Development and electrical properties of undoped polycrystalline silicon thin-film transistors

Abstract

Abstruct-The conduction mechanism and the origins of the leakage current in undoped channel polycrystalline silicon thin-film transistors fabricated under a variety of processing conditions were investigated. Leakage currents below 1 nA at drain-source voltages of 40 V were achieved in both n-type and p-type devices. The effective channel electron and hole mobilities were 75 and 42 cm2/Vs, respectively. Measured stage delay times for CMOS ring oscillators as a function of supply voltage agreed well with theoretical calculations. The effective carrier mobility was shown to have a minimum at a gate voltage corresponding to the point at which all traps are filled. Both dark and photo-induced leakage currents were determined to be controlled by generation from the grain boundary traps. The voltage drop across individual gates in multi-gated structures was investigated as a function of gate voltage. The use of multiple gates at high drain-source potentials was found to decrease both dark and photo-induced leakage currents.

Improved Electrical Performance and Reliability of Poly-Si TFTs Fabricated by Drive-In Nickel-Induced Crystallization with Chemical Oxide Layer

“…The chemical oxide layer did improve surface roughness (reduced implantation damage). The effective trap state density (N t ) was measured using Levinson and Proano's method, where N t is estimated from the slope of the linear segment of ln[I DS /(V GS À V FB )] versus 1/(V GS À V FB ) 2 at low V DS and high V GS , where V FB is defined as the gate voltage that yields the minimum drain current at V DS = 0.1 V. 16,17 As shown in Fig. 6, the N t of DICC-TFTs was 4.98 9 10 12 cm À2 , which was much less than that of MIC-TFTs (5.85 9 10 12 cm À2 ) and DIC-TFTs (6.69 9 10 12 cm À2 ).…”

Leakage current mechanisms in top-gate nanocrystalline silicon thin film transistors

“…1͑b͒, suggesting that it is determined by the intrinsic resistivity of the channel layer. 18 In this case, the dependence of the TFT channel dimensions on I L can help distinguish the resistive and junction leakage components, in which the former is proportional not only to 1 / L but also to W. Indeed, as we observe in Fig. 4, I L increases linearly with W. This resistive component, dominant at low V GS , is believed to be controlled by diffusion of holes in the bulk channel and, therefore, the minimum level of the resistive current is determined by their peak concentration.…”

A simpler 100-V polysilicon TFT with improved turn-on characteristics

“…With their high mobility and current drive, they also allow integration of peripheral circuits on the same large-area substrate, resulting in significant cost saving and improved reliability. For highvoltage operations, multiple-gated [3], [4], offset-gated [5]- [7], and hybrid structures [8] have been proposed as the highvoltage thin-film transistor (HVTFT) device structure. However, the maximum operation voltage is generally quite limited for multiple-gated HVTFT's (i.e., less than 40 V for double-gated devices).…”