Designing via-configurable logic blocks for regular fabric

Ran, Yajun; Marek-Sadowska, Malgorzata

doi:10.1109/tvlsi.2005.863196

Cited by 46 publications

(44 citation statements)

References 20 publications

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“…laid out in a regular manner, which can be mask-or in-field configured to implement specific logic functions. Several regular gate and logic arrays have been recently proposed to reduce the design risk due to increasing variability in current and future CMOS nodes, e.g., [8,[14][15][16].…”

Section: Discussion and Opportunitiesmentioning

confidence: 99%

Novel library of logic gates with ambipolar CNTFETs: Opportunities for multi-level logic synthesis

Jamaa

Mohanram

Micheli

2009

2009 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

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This paper exploits the unique in-field controllability of the device polarity of ambipolar carbon nanotube field effect transistors (CNTFETs) to design a technology library with higher expressive power than conventional CMOS libraries. Based on generalized NOR-NAND-AOI-OAI primitives, the proposed library of static ambipolar CNTFET gates efficiently implements XOR functions, provides full-swing outputs, and is extensible to alternate forms with areaperformance tradeoffs. Since the design of the gates can be regularized, the ability to functionalize them in-field opens opportunities for novel regular fabrics based on ambipolar CNTFETs. Technology mapping of several multi-level logic benchmarks -including multipliers, adders, and linear circuits -indicates that on average, it is possible to reduce both the number of gates and area by ∼ 38% while also improving performance by 6.9×.

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Section: Discussion and Opportunitiesmentioning

confidence: 99%

Novel library of logic gates with ambipolar CNTFETs: Opportunities for multi-level logic synthesis

Jamaa

Mohanram

Micheli

2009

2009 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

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“…Various regular fabrics have been proposed throughout the evolution of semiconductor industry, where some recent approaches are discussed in [10]- [12]. With the advent via programmable gate arrays [11] and logic-bricks [12], the performance gap is reduced. On the other hand, strict design rules, at 22-nm technology node and beyond, has led to cell layouts with arrays of gates with a constant gate pitch, which resemble a sea-of-gates layout style.…”

Section: Sea-of-tilesmentioning

confidence: 99%

“…The flexibility of building generic logic gates comes at a cost of area as well as routing overhead, thereby increasing the performance gap between application-specific integrated circuit (ASIC) and gate arrays. With the advent via programmable gate arrays [11] and logic bricks [12], the performance gap is reduced. On the other hand, strict design rules, at 22-nm technology node and beyond, has led to cell layouts with arrays of gates with a constant gate pitch, which resemble a sea-of-gates layout style.…”

mentioning

confidence: 99%

Layout Technique for Double-Gate Silicon Nanowire FETs With an Efficient Sea-of-Tiles Architecture

Bobba

Micheli

2015

IEEE Trans. VLSI Syst.

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Abstract-As we advance into the era of nanotechnology, semiconductor devices are scaled down to their physical limits, thereby opening up venues for new transistor channel materials based on nanowires and nanotubes. Transistors based on nanowires and nanotubes inherently exhibit ambipolar behavior. While technologists aim to suppress ambipolar behavior of these transistors, new design methodologies are proposed by exploiting the phenomenon of controllable polarity. In this paper, we propose regular layout fabrics, with an emphasis on silicon nanowires (SiNWs) as the candidate technology. A double-gate ambipolar SiNW field-effect transistor operates as p-type or n-type by electrically controlling the polarity of the second gate. We propose layout techniques to address gate-level routing congestion, as every transistor has two gates to route. Novel symbolic layouts, which are technology independent, are proposed for ambipolar circuits. In the second part of this paper, we present an approach for designing an efficient regular layout called sea-of-tiles (SoTs). A logic tile is essentially an array of prefabricated transistor-pairs grouped together. We design four logic tiles, which form the basic building block of the SoT fabric. We run extensive comparisons of mapping standard benchmarks onto the SoT fabric to find the optimum tile. This paper shows that SoT with Tile G2 and Tile G1h2 , on an average, outperforms the one with Tile G1 by 16% and 14% in area utilization, respectively.

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“…Implementing configuration bits using SRAM bits has the additional advantage that no extra processing steps beyond those needed to construct the other IP blocks on the SoC are required. Alternatively, in a structured ASIC fabric, the programmable switches in the connection fabric can be implemented using programmable metal and vias, in which connections between adjacent metal layers can be made by adding or removing metal [47], [48]. Typically, these programmable vias can be programmed only once (during fabrication), while programmable SRAM configuration bits can be programmed any number of times.…”

Section: ) Hardware Programmabilitymentioning

confidence: 99%

System-on-Chip: Reuse and Integration

et al. 2006

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| Over the past ten years, as integrated circuits became increasingly more complex and expensive, the industry began to embrace new design and reuse methodologies that are collectively referred to as system-on-chip (SoC) design.In this paper, we focus on the reuse and integration issues encountered in this paradigm shift. The reusable components, called intellectual property (IP) blocks or cores, are typically synthesizable register-transfer level (RTL) designs (often called soft cores) or layout level designs (often called hard cores). The concept of reuse can be carried out at the block, platform, or chip levels, and involves making the IP sufficiently general, configurable, or programmable, for use in a wide range of applications. The IP integration issues include connecting the computational units to the communication medium, which is moving from ad hoc bus-based approaches toward structured network-on-chip (NoC) architectures. Design-for-test methodologies are also described, along with verification issues that must be addressed when integrating reusable components.KEYWORDS | Analog intellectual property (IP); intellectual property (IP) cores; network-on-chip (NoC); platform-based design; programmable intellectual property (IP); system-onchip testing; system-on-chip verification; system-on-chip (SoC)

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Designing via-configurable logic blocks for regular fabric

Cited by 46 publications

References 20 publications

Novel library of logic gates with ambipolar CNTFETs: Opportunities for multi-level logic synthesis

Novel library of logic gates with ambipolar CNTFETs: Opportunities for multi-level logic synthesis

Layout Technique for Double-Gate Silicon Nanowire FETs With an Efficient Sea-of-Tiles Architecture

System-on-Chip: Reuse and Integration

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