Design Procedures for Three-Stage CMOS OTAs With Nested-Miller Compensation

Cannizzaro, S.O.; Grasso, Alfio Dario; Mita, R.; Palumbo, G.; Pennisi, S.

doi:10.1109/tcsi.2007.895520

Cited by 87 publications

(39 citation statements)

References 20 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Because of the particular conduct of the sub threshold operation, the outline methodology of a three stage OTA created for MOS devices in strong inversion can't be embraced [38] and, subsequently, a devoted technique must be characterized. After consideration the normal low power applications where subthreshold OTA are utilized, reduction of power dissipation for a desired speed execution, or proportionately, augmentation of speed execution for a given power utilization (i.e., current of biasing) is the primary target.…”

Section: Experimental Results Of Ota and Comparisonmentioning

confidence: 99%

Low Power Continuous-Time Delta-Sigma Modulators Using the Three Stage OTA and Dynamic Comparator

Gupta¹,

Gupta²,

Baghel³

2018

IJET

View full text Add to dashboard Cite

A second-order sigma delta modulator that uses an operational transconductance amplifier as integrator and latch comparator as quantizer. The proposed technique where a low power high gain OTA is used as integrator and another circuit called dynamic latch comparator with two tail transistors and two controlling switches are used to achieve high speed, low power and high resolution in second order delta sigma modulator. It enhances the power efficiency and compactness of the modulator by implementing these blocks as sub modules. A second order modulator has been designed to justify the effectiveness of the proposed design. Technology 180nm CMOS process is used to implement complete second order continuous time sigma delta modulator. We introduce the sub threshold three stage OTA, which is a way of achieving low distortion operation with input referred noise at 1 KHz is equal to the 2.2647pV/√ and with low power consumption of 296.72nW. A high-speed, low-voltage and a low-power Double-Tail dynamic comparator is also proposed. The proposed structure is contrasted with past dynamic comparators. In this paper, the comparator's delay will be investigated and systematic analysis are inferred. a novel comparator using two tail transistor is proposed, here circuitry of a customized comparator having two tail is changed for low power dissipation and also it operates fast at little supply voltages. By maintaining the outline and by including couple of transistors, during the regeneration strengthening of positive feedback can be maintained, this results in amazingly diminished delay parameter. It is investigated that in proposed design structure of comparator using two tail transistors, power consumption is reduced and delay time is also diminished to a great extent. The proposed comparator is having maximum clock frequency that is possibly expanded up to 1GHz at voltages of 1 V whereas it is dissipating 10.99 µW of power, individually. By using sub threshold three stage OTA and dynamic standard two tail latch comparator, designed second order sigma delta ADC will consume 29.95µW of power.

show abstract

Section: Experimental Results Of Ota and Comparisonmentioning

confidence: 99%

Low Power Continuous-Time Delta-Sigma Modulators Using the Three Stage OTA and Dynamic Comparator

Gupta¹,

Gupta²,

Baghel³

2018

IJET

View full text Add to dashboard Cite

show abstract

“…The transfer function of this circuit has numerous poles and zeros. However to simplify the analysis, some assumptions should be considered [1][2][3][4][5][6]. The first assumption treats with the values of C L , C C1 , and C C2 as elements, which are much larger than the parasitic capacitances seen at all nodes.…”

Section: Proposed Analysis: Three-stage Nested-miller-compensated Opampsmentioning

confidence: 99%

“…To proceed further, it is also essential to determine the modified formula of time-constant coefficient (n) with similar definition to Equation (6). The equivalent definition in third-order systems, however, is non-linear function of small-signal settling error, phase margin, and damping factor, namely…”

Section: H Aminzadehmentioning

confidence: 99%

See 1 more Smart Citation

Three‐stage nested‐Miller‐compensated operational amplifiers: Analysis, design, and optimization based on settling time

Aminzadeh

2011

Circuit Theory & Apps

View full text Add to dashboard Cite

SUMMARYIn analog signal-processing applications, settling performance of the employed operational amplifiers (opamps) is usually of great matter. Under low-voltage environment of modern technologies where only a few transistors are allowed to be stacked, three-stage amplifiers are gaining more interest. Unfortunately, design and optimization of three-stage opamps based on settling time still suffer from lack of a comprehensive analysis of the settling behavior and closed-form relations between settling time/error and other parameters. In this paper, a thorough analysis of the settling response of three-stage nestedMiller-compensated opamps, including linear and non-linear sections, is presented. This analysis leads to a design methodology which determines the circuit requirements for desired settling time/error. Based on settling time, it allows optimizations in power consumption and area.

show abstract

“…Therefore, increasing the channel length in order to boost the transistor output resistance is not a viable solution. A possible remedy to the gain reduction is the adoption of multistage amplifier topologies (cascading approach) [2][3][4][5][6][7]. By using simple low-voltage gain stages, the minimum supply requirement is preserved and voltage gain is increased.…”

Section: Introductionmentioning

confidence: 99%

0.9‐V CMOS cascode amplifier with body‐driven gain boosting

Monsurrò

Pennisi

Scotti

et al. 2008

Circuit Theory & Apps

Self Cite

View full text Add to dashboard Cite

SUMMARYThe body-driven variant of the gain-boosting technique is here exploited to design a CMOS transconductance amplifier with minimum supply below 1 V. When compared with the conventional gain-boosting technique, the proposed body-driven approach reduces the minimum supply requirement by two thresholds in a rail-to-rail amplifier exploiting two complementary input stage topologies. Simulations using a 130-nm process show that a 0.9-V power supply is adequate for a single-stage rail-to-rail amplifier providing a 56-dB gain, which is 18 dB higher than that achieved by the same architecture but using the traditional cascoding approach. The main drawbacks are that the solution requires a twin-tub process and an additional bias section.

show abstract

Design Procedures for Three-Stage CMOS OTAs With Nested-Miller Compensation

Cited by 87 publications

References 20 publications

Low Power Continuous-Time Delta-Sigma Modulators Using the Three Stage OTA and Dynamic Comparator

Low Power Continuous-Time Delta-Sigma Modulators Using the Three Stage OTA and Dynamic Comparator

Three‐stage nested‐Miller‐compensated operational amplifiers: Analysis, design, and optimization based on settling time

0.9‐V CMOS cascode amplifier with body‐driven gain boosting

Contact Info

Product

Resources

About