A true random number generator (TRNG) is a basic building block of many modern cryptographic systems. As field programmable gate array (FPGA) has a flexible architecture and low-cost test cycle, hence, it becomes an ideal platform for hardware implementation of digital systems. This paper presents an FPGA implementation of a high-speed TRNG that is based on a chaotic oscillator at 100 MHz frequency with speed of 1600 Mbps. The experimental resultsshow that the proposed generator is faster and more compact than the existing chaotic ring-oscillator-based TRNGs, and further, it is verified that the generated bit sequences pass all TRNG tests in National Institute of Standards and Technology (NIST SP 800-22). The proposed TRNG is implemented in two FPGA families: Nexys 4 DDR XC7A100TCSG-1 (Artix 7) and Basys 3 XC7A35T1CPG236C (Artix 7) Xilinx Vivado v.2017.3 design suite. KEYWORDS chaotic oscillator, field programmable gate array (FPGA), true random number generator (TRNG)
True random number generator is a basic building block of any modern secure communication and cryptography system. FPGA implementation of any system has a flexible architecture and low-cost test cycle. In this paper, we present an FPGA implementation of a high speed true random number generator based on chaos oscillator which gives optimize ratio of bit rate to area. The proposed generator is faster and more compact than the existing chaotic oscillator based TRNGs. The Experimental result shows that the proposed TRNG gives 1439 Mbps with optimizing the use of LUTs and registers. It is verified that the generator passes all the NIST SP 800-22 tests. The proposed TRNG is implemented in two FPGA families Nexus 4 (Artix 7) DDR XC7A100TCSG-1 and Basys 3 XC7A35T1CPG236C (Artix 7) using Xilinx Vivado v.2017.3 design suite.
Abstract-A wide slot antenna with Y shape tuning element is presented for wireless applications (GSM 1800, WiMAX, PCS and ITM-2000). The proposed antenna is fabricated on an FR-4 substrate (tan(δ) = 0.02, ε r = 4.3) with the thickness of 1.6 mm. On the top layer of the substrate, a 50 ohm microstrip line is fabricated which is terminated in Y shape tuning element. On ground plane, an irregular wide slot and triangular notch are etched. In addition, for performance improvement two triangular shaped parasitic slots are embedded on the ground plane. The proposed antenna is energized by the microstrip line. It exhibited the bandwidth of 127.55% from 1.15 GHz to 5.2 GHz for |S 11 | < −10 dB. Surface current distribution and radiation pattern at resonating frequencies 1.25, 1.9 and 4.2 GHz are analyzed. Impact of parameters on S 11 characteristic is also studied to know the behavior of the antenna.
Abstract-A high-driving class-AB buffer amplifier, which consists of a high-gain input stage and a pair of operational transconductance amplifier, is proposed. This paper presents a novel systematic offset minimization The high-driving capability is mainly provided by the folded amplifier class-AB CMOS operational amplifier. The proposed structure has a replica-gain circuit, generating a dc replica bias to the differential input stage, and providing differential gain as well as level conversion to drive the class-AB output stage .The circuit contains transconductance amplifiers in a rail to rail operation with both input and output stage based on the microwind technology and the offset due to device mismatch. An op amp low Cmos design is present in this paper. The circuit uses dual transconductance input pairs to achieve a rail-to-rail
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