Design Optimization of Three-Stacked Nanosheet FET From Self-Heating Effects Perspective

Rathore, Sunil; Jaisawal, Rajeewa Kumar; Kondekar, P. N.; Bagga, Navjeet

doi:10.1109/tdmr.2022.3181672

Cited by 37 publications

(7 citation statements)

References 34 publications

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“…Using the doped HfO 2 in the gate stacked, the deterioration in the electrical characteristics is mitigated compared to the BL FinFET. The frequency at which the gain of the FETs reaches the unity value is defined as the unity gain cut-off frequency ( f T ), given as [22,23]:…”

Section: Effect Of Varying Temperature On Analog/rf Merits Of Nc-finfetmentioning

confidence: 99%

Role of temperature on linearity and analog/RF performance merits of a negative capacitance FinFET

Jaisawal

Rathore

Gandhi

et al. 2022

Semicond. Sci. Technol.

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Temperature plays a decisive role in semiconductor device performance and reliability analysis. The effect is more severe in a Negative Capacitance (NC) transistor, as the temperature modulates the ferroelectric polarization, implicitly included by the Landau coefficients (α, β, γ) in TCAD. In this paper, through TCAD simulations, the role of varying ambient temperature is investigated in the linearity and analog/RF merits of NC-FinFET. The varying temperature modulates the carrier mobility, the semiconductor bandgap, and the Landau parameter (α). We analyzed the analog/RF and linearity metrics, such as total gate capacitance (Cgg), transconductance (gm), unity gain cut-off frequency (fT), the transconductance-frequency product (TFP), gain-bandwidth product (GBP), higher-order transconductance (gm2 and gm3), voltage intercept points (VIP2 and VIP3), third-order power intercept and intermodulation points (IIP3 and IMD3), and 1 dB compression point (CP) using well-calibrated TCAD models. Our analysis reveals that these parameters are strongly dependent on temperature and the negative capacitance (NC) span (defined by using S-curve) shrinks with the rise in temperature. Finally, a source follower and three-stage ring oscillator are designed to test the frequency compatibility of the AC simulation for varying temperatures.

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Section: Effect Of Varying Temperature On Analog/rf Merits Of Nc-finfetmentioning

confidence: 99%

Role of temperature on linearity and analog/RF performance merits of a negative capacitance FinFET

Jaisawal

Rathore

Gandhi

et al. 2022

Semicond. Sci. Technol.

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“…An NSFET is a GAA structure with poor heat dissipation compared to bulk-FinFET devices with bulk silicon substrates [ 18 ]. Furthermore, to improve the mobility of P-type NSFETs, NSFET devices with advanced technology often use SiGe in the source and drain, but the thermal conductivity of SiGe is low, which aggravates the self-heating effect in NSFETs [ 19 , 20 , 21 ].…”

Section: Introductionmentioning

confidence: 99%

Interaction of Negative Bias Instability and Self-Heating Effect on Threshold Voltage and SRAM (Static Random-Access Memory) Stability of Nanosheet Field-Effect Transistors

Li,

Shao,

Wang

et al. 2024

Micromachines

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In this paper, we investigate the effects of negative bias instability (NBTI) and self-heating effect (SHE) on threshold voltage in NSFETs. To explore accurately the interaction between SHE and NBTI, we established an NBTI simulation framework based on trap microdynamics and considered the influence of the self-heating effect. The results show that NBTI weakens the SHE effect, while SHE exacerbates the NBTI effect. Since the width of the nanosheet in NSFET has a significant control effect on the electric field distribution, we also studied the effect of the width of the nanosheet on the NBTI and self-heating effect. The results show that increasing the width of the nanosheet will reduce the NBTI effect but will enhance the SHE effect. In addition, we extended our research to the SRAM cell circuit, and the results show that the NBTI effect will reduce the static noise margin (SNM) of the SRAM cell, and the NBTI effect affected by self-heating will make the SNM decrease more significantly. In addition, our research results also indicate that increasing the nanosheet width can help slow down the NBTI effect and the negative impact of NBTI on SRAM performance affected by the self-heating effect.

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“…Moreover, the QGFETs suffer from corner effects. Owing to the challenges presented in above devices, the GAA structures has gained traction due to their ability to provide excellent electrostatic control, mitigating issues associated with SCEs, and improving the transistor's overall performance [15,16]. The Cylindrical GAA FET is characterized by its unique architecture, in which the gate electrode fully surrounds the channel region of the transistor.…”

Section: Introductionmentioning

confidence: 99%

An analytical drain current modelling of DMGC CGAA FET: A circuit level implementation

Mudidhe,

Nistala

2023

Phys. Scr.

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The GAA FET has emerged as a promising device due to its excellent control over short-channel effects and improved electrostatic control. This manuscript presents the analytical modelling for the Dual Material Graded Channel (DMGC) Cylindrical GAA FET to characterize the drain current in linear, saturation, as well as subthreshold regions. The model incorporates the effect of supply voltage, radius, and thickness of oxide layer on the device enabling a comprehensive analysis of the device behaviour. The influence of subthreshold swing is also presented. Next, the analysis is extended to investigate the important analog performance parameters that includes transconductance and output conductance. The validation of the analytical model across a wide range of operating conditions with the simulated data is performed and observed to be a close match. Building upon the insights gained from the analytical modelling, a common source amplifier based on the DMGC CGAA FET is designed. The amplifier's performance has been optimized by carefully selecting the biasing conditions and a maximum gain value of 7.745 is achieved. Further, an improvement of 42.28% in output voltage is observed for DMGC in comparison with SMGC making it a promising device for high-performance integrated circuit design.

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Design Optimization of Three-Stacked Nanosheet FET From Self-Heating Effects Perspective

Cited by 37 publications

References 34 publications

Role of temperature on linearity and analog/RF performance merits of a negative capacitance FinFET

Role of temperature on linearity and analog/RF performance merits of a negative capacitance FinFET

Interaction of Negative Bias Instability and Self-Heating Effect on Threshold Voltage and SRAM (Static Random-Access Memory) Stability of Nanosheet Field-Effect Transistors

An analytical drain current modelling of DMGC CGAA FET: A circuit level implementation

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