Design of ripple carry adder using CMOS output wired logic based majority gate

Sarkar, Mili; Taki, G. S.; Prerna,; Sengupta, Rimi; Ray, Soham Nandi

doi:10.1109/iemecon.2017.8079617

Cited by 5 publications

(2 citation statements)

References 15 publications

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“…Where N is the binary digit bits. In (3) shows that the path delay of carry output required N-bit delays, farther one more gate delay time. This describes, why the delay time of the proposed method is about 27% time less than that in the RCA.…”

Section: Design Circuit Of Pipelined Carry Addermentioning

confidence: 99%

“…The critical path delay is determined by the longest pathway through the adder circuit. Therefore, the critical path delay of N-bit adders is determined by three gate delays of the first bit adder and to ripples in two gate delays of each of the next adders [1], explaining why it is called 'ripple carry adder (RCA)' [2], [3]. The critical path delay is calculated using (1).…”

Section: Introductionmentioning

confidence: 99%

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A novel pipelined carry adder design based on half adder

Alkurwy

Hameed

2022

IJEECS

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<span lang="EN-US">A new design of binary parallel adder circuit is presented in this paper. The pipeline technique is applied to implement a group of a half adder (HA) blocks to architect the proposed adder. The pipelined carry adder (PCA) method is suitable for carrying out the desired adder by using the HA circuits of XOR and AND gates. The applied technique reduces the critical path delay by 27% compared with the ripple carry adder (RCA) and relatively lowers logic gates by 55% compared with the carry look-ahead adder (CLA). The coded design of the proposed circuit is implemented and simulated on the Cyclone IV FPGA kit platform. Results show that the circuit needs a 7.69 ƞ Sec delay time to provide the output values. The suggested PCA circuit is more attractive than the conventional ripple carry adder for future electronic applications. </span>

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Section: Design Circuit Of Pipelined Carry Addermentioning

confidence: 99%