This paper presents a novel, memoryless, read-only memory (ROM) design architecture for a direct digital frequency synthesizer (DDFS). A pipelining technique is proposed to increase the phase accumulator (PA) throughput.However, this technique increases the number of registers as the pipeline stages increase. The shifted clocking technique is used to reduce the pipelined PA registers. The wave symmetry technique is applied to store (0: π /2) of the sine wave.The ROM is partitioned into three four-bit sub-ROMs based on the angular decomposition technique and trigonometric identity. A novel approach of memoryless ROM design technique is proposed and implemented in the design of a 24-bit DDFS system that replaces the conventional ROM. Replacing the memoryless sub-ROM circuits, instead of the conventional 12-bit ROM, reduces power consumption and area dimension. As a result, compared to the conventional ROM circuit, the values of area dimension and dynamic power are reduced by 15% and 14.8%, respectively.
<p><span>A novel approach of multiplier design is presented in this paper. The design </span>idea is implemented based on binary coded decimal (BCD) decoder to seven segment display, by computing all the probability of multiplying 3 3 binary digits bits and grouping in table rows. The obtaining of the combinational logic functions is achieved by simplified the generated columns of [A<sub>5: </sub>A<sub>0</sub>]<sub>, </sub>using a Karnaugh map. Then, the 3 3-bits multiplier circuit is used to implement the 6x6- and 12x 12-bit multipliers. Comparing with a conventional multiplier, the proposed design outperformed in terms of the time delay by a 32% and 41.8% respectively. It is also reduced the combinational adaptive look-up-tables (ALUTs) by 24.6%, and 46% for both multipliers. Both overmentioned advantages make the proposed multipliers more attractive and suitable for high-speed digital systems</p><p> </p><p> </p><p> </p><p> </p><p> </p><p> </p>
A Low Power Compressed ROM Look-up table has been presented in this paper to achieve low power consumption of the direct digital frequency synthesizer as well small core size. The quarter wave symmetry technique is used to store only one quarter of the sine wave. The suggested 12-bit compressed ROM designed consists of three 4-bit sub-ROMs based on an angular decomposition technique and trigonometric identity. Exploiting the advantages of sine-cosine symmetrical attributes together with XOR logic gates, one sub-ROM block can be removed from the design. These techniques, compressed the ROM into 368 bits. The ROM compressed ratio is 534.2:1, with only two adders, two multipliers, and XOR-gates with high frequency resolution of 0.029 Hz.
Keywords; direct digital frequency synthesizer (DDFS); ROM Look-up table (ROM LUT), phase accumulator (PA).I.
This paper introduces a new technique of designing a read-only memory (ROM) circuit, namely; memory-less ROM as a novel approach to designing the ROM lookup table (LUT) circuit for use in a direct digital frequency synthesizer (DDFS). The proposed DDFS design uses the pipelined phase accumulator (PA) based on the kogge-stone (KS) adder. Verilog HDL programming is encoded on the architecture circuit of pipelined PA and contrasted with other PA based on various adders. The obtained results define the KS adder as having good capabilities for improving the throughput. In addition to the quarter symmetry technique, the built memory-less ROM to obtain the quarter sine amplitude waveform is proposed and implemented in the DDFS system. The implementation of the proposed technique replaces the necessary ROM registers (384 D flip-flops) and multiplexers with simple logic gate circuits instead of traditional ROMs. This technique would reduce the area size and cell count by 56% and 32.6% respectively.
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