A novel approach of multiplier design based on BCD decoder

Abstract

<p><span>A novel approach of multiplier design is presented in this paper. The design </span>idea is implemented based on binary coded decimal (BCD) decoder to seven segment display, by computing all the probability of multiplying 3 3 binary digits bits and grouping in table rows. The obtaining of the combinational logic functions is achieved by simplified the generated columns of [A<sub>5: </sub>A<sub>0</sub>]<sub>, </sub>using a Karnaugh map. Then, the 3 3-bits multiplier circuit is used to implement the 6x6- and 12x 12-bit multipliers. Comparing with a conventional multiplier, the proposed design outperformed in terms of the time delay by a 32% and 41.8% respectively. It is also reduced the combinational adaptive look-up-tables (ALUTs) by 24.6%, and 46% for both multipliers. Both overmentioned advantages make the proposed multipliers more attractive and suitable for high-speed digital systems</p><p> </p><p> </p><p> </p><p> </p><p> </p><p> </p>

Method of the adaptive decoding of self-orthogonal codes in telecommunication

“…Detailed research of advantages of multi-threshold decoding in a binary erasure channel is provided in [15]. The represented paper complements the research of authors covered in [18][19][20][21].…”

“…The results of design of multi-threshold decoders in the telecommunication channels with multiposition phase shift keying in the case of exportation of hard decision by a demodulator are presented in Figure 4 and Figure 5. In researching the block and convolved self-orthogonal codes with rates 4/5, 7/8 (d=9) are used in the case of signals employment of type 16QAM and 256QAM (hard decision of demodulator) [5,20,21]. Codes in minimum probability of propagation of errors and n=500 were used as long codes but comparison was with RS codes [6].…”

“…The offered algorithm gives the possibility to change adaptive coder and decoder parameters for the state of telecommunication channel, relying on intensity of noises. Algorithm of RLS adaptation (Recursive Least Square) is used for the lead through of adaptation with the purpose of SNR determination in a telecommunication channel [20][21][22][23][24]. Let the entrance discrete random signal х(t) be processed with the nonrecursive discrete filter of N order.…”

An area efficient memory-less ROM design architecture for direct digital frequency synthesizer

“…The basic concept of BCD-to-7-segment decoder is explained as follows: BCD is used to provide the (0-9) numbers listed in the binary digits' rows, whereas the listed column lines based on the binary digits' rows is used to provide the segment display. The memory-less ROM replacement circuit is designed on the basis of the 7-segment display and the technique applied in [17][18][19]. The suggested quarter sinewave values, which are listed in 6-bit binary digits in rows 0-63 (X5:X0), are used as a counter of the memory-less ROM circuit.…”

Reversible logic in pipelined low power vedic multiplier

“…Vedic mathematics specifies 16 sutras (Formulae) and sub-sutras (Sub-formulae) which can be employed in different arithmetic calculations [2]. It is well-known that with the techniques laid out in Vedic mathematics, the calculations are got at a faster rate than conventional mathematical techniques [3]. The Urdhava Tiryakbhyam (UT) sutra is the most commonly used Vedic formula for multiplication.…”