Reversible logic in pipelined low power vedic multiplier

Abstract

<span>With an ever growing demand for low-power devices, it is a general trend to search for ways to reduce the power consumption of a system. Multipliers are an important requirement in applications linked to Digital Signal Processing, Communication Systems, Optical Computing, Nanotechnology, Low-Power Very Large Scale Integration and Quantum Computing. Conventional mathematics makes multiplication a very long and time consuming process. The use of Vedic mathematics has led to great reduction in the time required for such calculations. The excessive use of Urdhava Tiryakbhyam sutra in multiplication surely proves its effectiveness and simplicity in this domain. This sutra supports the process of pipelining, a method employed in reduction of the power used by a system. Reversible logic has been gaining demand due to its low-power capabilities and is currently being used in many computing applications. The paper proposes two multiplier systems: one design employs the Urdhava Tiryakbhyam sutra along with pipelining and the second uses reversible logic gates into the first design. These proposed systems provide very less delay for result computation and low hardware utilization when compared to non-pipelined Vedic multipliers.</span>

Pipelined vedic multiplier with manifold adder complexity levels

“…There are two steps followed in multiplication: partial product generation and partial product accumulation [24,25]. The changes in the processing method of these two steps result in difference in throughput of the multiplier.…”

Low Power 32 x 32 – bit Reversible Vedic Multiplier

“…2. When the input, Z, is kept constant at "0", the output R is the product of the two other inputs [16]. This is shown in Table I.…”